[time-nuts] Understanding Oliver Collins Paper "Design of Low Jitter Hard Limiters"

Magnus Danielson magnus at rubidium.dyndns.org
Thu Aug 23 19:04:53 EDT 2012


On 08/24/2012 12:07 AM, Bob Camp wrote:
> Hi
>
> In general, saturated logic (TTL / CMOS) will do better than non-saturated (ECL / LVDS). Faster with saturated generally = better, provided it's silicon. Once you go to high mobility semiconductors the 1/f noise picks up. Yes, you need a quiet supply. How quiet is going to depend on your edge rates, input frequencies, phase noise offsets, the coupling circuit, and the logic used. Put another way - you need to test your circuit. There are bits and pieces of that very limited summary scattered across several hundred papers and data sheets.

NIST has only made a few papers on it, and to some degree it is 
inconclusive. Also, it doesn't give good hints on more current logic as 
it was made ages ago.

Cheers,
Magnus




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