[time-nuts] Understanding Oliver Collins Paper "Design of Low Jitter Hard Limiters"

Jerry Mulchin jmulchin at cox.net
Thu Aug 23 01:03:28 UTC 2012


The amount of jitter verses logic family is all over the place as well.
Take a look at an LS verses an HCT vs an S family and you will see what I mean.
Some of them are very nasty, and are not all created equally.

Jerry

At 09:58 AM 8/22/2012, you wrote:
>I was not measuring cycle to cycle jitter but the input to output
>jitter of a TTL gate itself when used as part of a delay circuit.  The
>input circuit and input waveform to the gate are very similar to what
>would be expected in a sine wave zero crossing detector.
>
>Using a 7S11/7T11 in sequential sampling mode, I could see the jitter
>fine on any analog 7000 series oscilloscope but to get a nicer photo,
>I used a 7834 in variable persistence mode.  The trigger occurs about
>80ns before the displayed fast rise pulse.  Most of the jitter is a
>product of the low power supply rejection of the TTL gate and input
>circuit.
>
>http://www.banishedsouls.org/c2df3757f1/PG506/PDJ%20Test%201b%20-%201.jpg
>
>Using hard limiting before the zero crossing detector will relax the
>design of the later significantly.  Differential signal paths would
>help considerably as well.
>
> From going through the manuals and specifications, I am just not sure
>the TDS220 or TDS3012 has the time base resolution necessary to
>compare the jitter from the two different designs.  On my 2440, it was
>very difficult to see any difference between no jitter and the jitter
>in the example I linked above.
>
>On Wed, 22 Aug 2012 15:44:10 +0200, Azelio Boriani
><azelio.boriani at screen.it> wrote:
>
>>According to
>>
>>http://cp.literature.agilent.com/litweb/pdf/5989-8794EN.pdf
>>
>>the real time sampling scope (like the TDS220 or TDS3012) can measure cycle
>>to cycle jitter directly, whereas the equivalent time sampling has only one
>>sample each trigger and a little delay on the sampling point for the next
>>trigger. The displayed waveform is a sort of "sum" of more than one cycle
>>and now I can't figure out what type of picture this can give. The TDS3012
>>has also the advantage of the Digital Phosphor behavior that can be useful
>>for the jitter analysis. Maybe a stable timebase and low jitter external
>>trigger input are essential. Unfortunately the TDS3012 has a 200ppm
>>timebase...
>>
>>On Wed, Aug 22, 2012 at 2:54 PM, David <davidwhess at gmail.com> wrote:
>>
>>> Do you mean with a 7404 hex inverter?  I actually did something like
>>> this recently while adding a 75ns pre-trigger pulse to an existing
>>> fast rise pulse generator.
>>>
>>> The pre-trigger pulse ended up having significant pattern dependant
>>> jitter caused by the adjacent TTL divider chain modulating the supply
>>> voltage and the poor power supply rejection of the 7404.  I was easily
>>> able to see the jitter on my 7T11 sampling oscilloscope but on my 2440
>>> (20 GS/sec equivalent time sampling), it was barely perceptible if
>>> that despite ideal conditions.  The peak to peak jitter was about
>>> 100ps.
>>>
>>> As far as I could tell from the available online documentation, the
>>> TDS220 and TDS3012 have relatively low sample rates and do not support
>>> equivalent time sampling so I would expect them to show even less than
>>> my 2440.
>>>
>>> On Wed, 22 Aug 2012 11:55:11 +0200, Azelio Boriani
>>> <azelio.boriani at screen.it> wrote:
>>>
>>> >In your opinion, if I build a 7404 ZCD and a hard limiter one, can I see
>>> >the jitter difference on a simple 'scope (Tek TDS220 or TDS3012) or do I
>>> >need the Wavecrest SIA3000?
>>> >
>>> >On Wed, Aug 22, 2012 at 1:37 AM, Bob Camp <lists at rtty.us> wrote:
>>> >
>>> >> Hi
>>> >>
>>> >> Since the Collins approach "tunes" the system for a single frequency
>>> input
>>> >> (more or less), the approach is probably not the best for a "many
>>> decades"
>>> >> sort of frequency range. There are a number of things that he alludes
>>> to in
>>> >> the paper, but does not directly address. The most obvious is the
>>> >> temperature dependance of the "stuff" the system is made of. Another is
>>> the
>>> >> simple fact that a non-clipping linear amplifier is likely the best
>>> choice
>>> >> for a first stage, provide the input is not already near clipping.
>>> >>
>>> >> Bob
>>> >>
>>> >> On Aug 21, 2012, at 12:50 PM, raj_sodhi at agilent.com wrote:
>>> >>
>>> >> > Hello everyone,
>>> >> >
>>> >> > I am new to this forum.
>>> >> > It looks like a lively discussion on various topics.
>>> >> >
>>> >> > A colleague of mine here at Agilent pointed me to this paper entitled
>>> >> "The Design of Low Jitter Hard Limiters" by Oliver Collins. In Bruce
>>> >> Griffiths' precision time in frequency webpage, this paper is described
>>> as
>>> >> "seminal."
>>> >> > (http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html)
>>> >> >
>>> >> > Since I'm trying to create a limiter that will accept frequencies
>>> >> ranging from 1 MHz to 100 MHz, I thought it would be good to understand
>>> the
>>> >> conclusions of this paper (if not the mathematics as well).  The
>>> >> mathematics turned out to be quite challenging to decode. Has someone on
>>> >> this forum unraveled the equations? It appears Collins has
>>> recommendations
>>> >> on the bandwidth and gain of a jitter minimizing limiter, and then
>>> extends
>>> >> this analysis to provide the bandwidth and gain of a cascade of
>>> limiters.
>>> >>  But the application is still fuzzy.  In figure 5, he shows a graph
>>> showing
>>> >> the dependence of jitter on crossing time.  Is the crossing time
>>> (implied
>>> >> by equations 7) considered a design parameter one can vary? Also, on
>>> figure
>>> >> 4, the "k" parameter has been varied to show the rising waveform as a
>>> >> function of "k".  The threshold is always assumed to be 0.5.  So could
>>> "k"
>>> >> be related to "tau", the time constant of the RC filter?
>>> >> >
>>> >> > Thanks in advance for all your help.
>>> >> >
>>> >> > Yours
>>> >> >
>>> >> > Raj
>>> >> >
>>> >> >
>>> >> >
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Jerry Mulchin





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