[time-nuts] GPSDO Alternatives

Bob Camp lists at rtty.us
Fri Dec 7 12:05:18 UTC 2012


Hi

To make things play nice, you would like to have the timer counters reset at a specified point. That way the math all works out nicely.

Bob

On Dec 7, 2012, at 12:18 AM, Hal Murray <hmurray at megapathdsl.net> wrote:

> 
> lists at rtty.us said:
>> That would be an input capture rather than an interrupt.
> 
> Thanks.  Yes, that's the term I was trying to remember.
> 
> 
> lists at rtty.us said:
>> To be useful, you need an input capture that:
>> 1) Runs at a fast enough clock (1 GHz would be nice)
>> 2) Has enough bits to get to 1 pps (say 32 bits)
>> 3) Has a built in period set, so the hardware works without a lot of silly stuff 
> 
> What do you mean by "period set"?
> 
> (I did a bit of googling, but didn't hit anything close to pay dirt.)
> 
> My expectation is that the counter/timer just counts on the local/CPU clock 
> or some sub-multiple of that.  When the external signal makes a low-to-high 
> transition, the value in the counter is copied into a holding register and 
> sets a status bit that may generate an interrupt.  The counter just keeps 
> counting through overflows and such.
> 
> ----------
> 
> The enough-bits from [2] above can be partially implemented in software.  
> When the counter overflows, it sets a status bit and maybe generates an 
> interrupt.  The software keeps the high bits in memory.  When it sees that 
> status bit, it bumps that counter.
> 
> Getting everything right is not simple.
> 
> There is a standard recipe for reading a hardware counter that lives in two 
> registers.  You read high, low, high.  If the two high readings match, the 
> answer is (either) high and low.  If not, try again.
> 
> Some hardware supports a hack to latch the high when you read the low.
> 
> 
> -- 
> These are my opinions.  I hate spam.
> 
> 
> 
> 
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