[time-nuts] Comparing PPS from 2 GPS units

M. Simon msimon6808 at yahoo.com
Mon Dec 17 20:04:29 UTC 2012

Nice pulse delay generator:


The article that goes with it:


The delay is analog - charging a capacitor until it crosses a threshold. So I don't know if it is good enough. But I did find it interesting. The order of the delay is 1 to 250 uSec. Faster parts would get you into shorter delays. 

If you had two of these operating on a common trigger...


Engineering is the art of making what you want from what you can get at a profit.

> From: David <davidwhess at gmail.com>
>To: Discussion of precise time and frequency measurement <time-nuts at febo.com> 
>Sent: Monday, December 17, 2012 6:56 PM
>Subject: Re: [time-nuts] Comparing PPS from 2 GPS units
>On Mon, 17 Dec 2012 10:19:43 -0800, Hal Murray
><hmurray at megapathdsl.net> wrote:
>>> A fifth solution is to use a pulse delay generator like a DG535. I use this
>>> to create high-resolution early/late 1PPS sync pulses. They show up on eBay,
>>> but aren't cheap. For bargains, watch for older model programmable pulse
>>> delay generators by BNC (Berkeley Nucleonics Corporation).
>>Thanks.  Those are more $$$ than I'm interested in right now, but might be a 
>>useful tool sometime in the future.
>>Another approach is to use a scope: trigger on one PPS and adjust the delay 
>>(which might be negative) and sweep speed so you can see the other PPS 
>>signal.  Maybe I'll play with this to see what sort of results I can get.
>>> Lastly, there are cute little delay boxes (www.ebay.com/itm/150962422699)
>>> that might work. Not sure how stable they are at the ns level. But it would
>>> be fun to measure. If someone opens one of these please tell us if it's a
>>> coil of wire, some kind of LRC filter delay, or if they use those Dallas
>>> delay chips. Which is another solution for you -- google or eBay search for:
>>> silicon delay line. 
>>You can make a reasonable delay line by using the lumped circuit 
>>approximation for the L and C for the appropriate impedance transmission 
>>line.  I assume that's what's in the delay boxes.  I should try that 
>>sometime.  Thanks for the reminder.
>>The delay chips I've looked at before used gate delays.  I think they were 
>>Motorola rather than Dallas.  I just poked at a few Maxim data sheets.  I 
>>didn't find out how they implemented the delays.
>>I think some of the clock recovery chips tune delays by tweaking the 
>>threshold voltage.
>I have been testing just using adjustable RC delays into a logic gate
>to generate pretrigger pulses for sampling oscilloscopes.  Accuracy
>depends on a complete reset of the capacitor and tracking between the
>RC charge voltage and gate threshold voltage.  Worst cast jitter for
>TTL has been in the 100s of picoseconds range because of supply
>voltage sensitivity.  Different families of TTL and CMOS logic all
>performed about the same.
>Here is the jitter measurement that came from the RC logic gate delay
>Much better is to use a differential comparator or differential input
>ECL which solves the threshold variation errors and a fast (it really
>isn't all that fast) ramp generator with a precision reset.  The
>differential input allows the ramp rate and threshold voltage to be
>linked allowing ratiometric operation to reject power supply or
>reference voltage variation and noise.
>My next pretrigger generator is going the differential comparator or
>differential ECL route with a fast ramp and precision reset.  I expect
>jitter to be significantly better than 10s of picoseconds for delays
>up to about 100 nanoseconds.  If I get down to 10 picoseconds of
>jitter, I will be happy since I have no real way to measure much below
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