[time-nuts] Questions about TAC frontend, and some measurements
bruce.griffiths at xtra.co.nz
Tue Dec 25 22:15:03 UTC 2012
The simplest (lowest part count and least number of power supplies)
consists of a tristate buffer driving an RC circuit.
The PPS signal is connected directly to the buffer input whilst the
output of the PPS synchroniser (at least 2 stages to minimise the
probability of metastabilty at the synchroniser output) drives the
buffer tristate control input.
The RC network starts charging when the PPS signal goes high and stops
when the synchroniser output goes high.
The capacitor charging is nonlinear but this is easily corrected in
The capacitor is connected between the input of a capacitive charge
redistribution ADC and ground.
Software correction for the effect of charging the charge ADC input
capacitance is also required.
Suitable fast single gate tristate drives are readily available.
With low tempco resistors and capacitors the TAC gain tempco can be
200pmm/C or less.
The only disadvantages are the increased software complexity and the
need for an extra bit of ADC resolution to maintain TAC resolution.
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