[time-nuts] Questions about TAC frontend, and some measurements
lists at rtty.us
Wed Dec 26 13:34:55 UTC 2012
You should check out the leakage of a typical tristate buffer. It's specified at a level that makes it easy to test. Most of the parts you find have very low leakage. Varicap diodes are similar in that respect, the leakage of real parts is much lower than the 1 ua you see on the old specs.
The likely qualifier on all that is "at room temperature". I'm sure the leakage goes a bit nuts as the parts get to 125C.
On Dec 26, 2012, at 5:26 AM, Fabio Eboli <fabioeb at quipo.it> wrote:
> Hello, hope you all had a happy Christmas.
> Back to the topic.
> Bob Camp asked:
>> One very simple question - how good would it do if you just did it all with logic gates? Tri-state buffers and things like that….
>> Now that you are up to a 100 to 200 ns long pulse, a lot of the fiddly stuff about "can't get a 2 ns pulse through it" goes away.
>> I'm not suggesting you tear up what you have. It's just something else to try and compare
> Bob, are you hinting to something like the last mail from Bruce?
> I.e. to use a tristate buffer to charge the capacitor?
> If not can you explicit what are you thinking? :)
> Thanks also to Alan Melia and Tom Miller for the details about
> bjt saturation .
> Bruce, about the tempco of the current generators,
> There is the led in series with a BE junction.
> The blue leds should have a tempco in mV per °C similar
> to th BE junction, dont know the red ones.
> Would it be better to use something like a 4.7 or 5.1V
> zener? If I remember correctly these zener voltage
> shuld cancel most of the BE tempco.
> And what about a TL431 instead of the led+bjt?
> The Avago diodes are pretty costly :)
> Is that circuit working like the internals of ECL logic
>> The simplest (lowest part count and least number of power supplies)
>> consists of a tristate buffer driving an RC circuit.
>> The PPS signal is connected directly to the buffer input whilst the
>> output of the PPS synchroniser (at least 2 stages to minimise the
>> probability of metastabilty at the synchroniser output) drives the
>> buffer tristate control input.
> A 2 stage syncronizer is composed of 3 FF?
> I.e. clock in parallel to 3 FF, PPS to the
> first D, Q from the first to D of the second,
> same from the second to the thid, and Q from
> the third to out. Let's assume that the inputs
> from PPS and 10MHz are fast enough, what can still
> generate metastability? Setup time violation?
>> The RC network starts charging when the PPS signal goes high and
>> stops when the synchroniser output goes high.
>> The capacitor charging is nonlinear but this is easily corrected in software.
>> The capacitor is connected between the input of a capacitive charge
>> redistribution ADC and ground.
>> Software correction for the effect of charging the charge ADC input
>> capacitance is also required.
> I see you are stressing the fact of using a capacitive charge
> redistribution adc. I dont know much about the internals
> of the ADC devices, can you suggest a partnumber for an example?
>> Suitable fast single gate tristate drives are readily available.
>> With low tempco resistors and capacitors the TAC gain tempco can be
>> 200pmm/C or less.
>> The only disadvantages are the increased software complexity and the
>> need for an extra bit of ADC resolution to maintain TAC resolution.
> The 3-state buffer + R-C seem an elegant solution for a microcontroller
> based thing, I'v given an eye to logic buffers, and seem that all
> suggest that the Hi-Z state leackage current is not very well
> specified, but something around 1uA, that means that cap's voltage after
> the pulse can rapidly (and unpredictabily?)change due to leackage.
> I imagine also that the leackage of the buffer will vary with temperature.
> The ADC of the micro is pretty fast, I shuld check the datasheet
> but I remember around 1uS per conversion, what would happen connecting
> directly the micro ADC to the charged cap? And sync the ADC to sample
> immediately (few uS) after the pulse. Could the loading from the
> s/h capacitance be corrected in fw?
> By the way, I updated my miserable schematic, I tried a simple
> mod to avoid the saturation of the switches. Only because I had
> it already built: http://pastebin.com/9VHkhmSv
> Now I'm chasing the origin of the drift variation, logging
> the temperatures and voltages. More on this as soon as I
> have some data.
> Thank you all,
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