[time-nuts] An embedded NTP server

Bob Camp lists at rtty.us
Fri Dec 28 18:01:39 UTC 2012


Much easier to simply use a cheap chip set (as in sub $3) that supports 1588 packet time stamping. It's doing everything you would need to do as far as packet time of arrival. The heavy lifting would all be in the area of porting that data into the NTP server.


On Dec 28, 2012, at 12:34 PM, Chris Albertson <albertson.chris at gmail.com> wrote:

> On Thu, Dec 27, 2012 at 1:36 AM, Hal Murray <hmurray at megapathdsl.net> wrote:
>> It would be interesting to see what ntpd would do on a system with a very
>> good clock and/or what you could do to the code/heuristics to take advantage
>> of a stable clock.
> I've read reports of people who have un-soldered the crystal from a
> motherboard and replaced it with a connection to somethig much more
> stable.  The result is a more stable clock adjustment but not a more
> accurate NTP server.   The bottleneck is not the oscillator.  It is
> the uncertiantly in the interrupt latency on the PPS.
> If you want a much improved NTP server you need to build an external
> nanosecond counter and then modify NTP and the OS to read this counter
> rather than the internal one.    So this could not work on Windows or
> any closed source OS.   Then you use a hardware latch to shapshot the
> external counter when the PPS happens.    The current system does the
> snapshot inside the interrupt handler, then sets a bit to indicate a
> new sample is available, the captured count is read by the background
> process.
> Building a counter that runs at 1GHz is not to hard but connecting it
> so the computer's OS can read it with very low latency is harder.
> Maybe the counter is built on a PCI card?  It couldn't go on a USB
> port
> One idea that I like is to first get a large FPGA.  Then you load in a
> "soft CPU" and then you run an OS and NTP on the soft CPU.   Inside
> the softCPU the counter is implemented like it is in a real CPU but
> you can add the ability for a PPS to "latch" it.  Basicaly you move
> the interrupt handler to hardware.     The trick is if you can get
> good enough performance out of the soft CPU?    There is some
> intelectual property problems with some soft CPS but I'm pretty sure
> there are free SPARC CPS you can use and SPARC is ideal for this as it
> can run BSD Unix.
> --
> Chris Albertson
> Redondo Beach, California
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