[time-nuts] Testing the TAC, and a question about ADEV

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Dec 28 18:53:47 UTC 2012


One potential source of non monotonicity is the ADC particularly those 
embedded in a microprocessor.
The only cure being to either use an external ADC that is monotonic or 
truncate the ADC result until it's monotonic.

Varying the synchroniser clock frequency (a 2:1 range  should suffice to 
cover the range of interest) should allow non monotonic behaviour to be 
detected.
Otherwise one has to resort to using calibrated delay lines.

Bruce

Bob Camp wrote:
> Hi
>
> The statistical fill approach is a cute way to go. The gotcha comes in when you have a structure that *may* not be monotonic.
>
> Bob
>
> On Dec 28, 2012, at 1:04 PM, Bruce Griffiths<bruce.griffiths at xtra.co.nz>  wrote:
>
>    
>> Fabio Eboli wrote:
>>      
>>> Hello
>>>
>>> How could I test the time to analog converter
>>> we talked few posts ago?
>>> Something that can be done with things I have
>>> or can easily find.
>>>        
>> One method is to use a statistical fill the buckets technique to measure the linearity.
>> To do this one needs to use an incoherent source to trigger the interpolator and plot a histogram of the results.
>> A noisy RC oscillator would be useful for this but care should be taken to avoid injection locking.
>> To achieve useful measurement in a reasonable time interval a trigger rate somewhat greater than 1Hz is required.
>> If the interpolator has 1024 time delay bins then ~ 100,000 trigger events are required to achieve a bin width measurement error of 10%.
>>
>> Otherwise a series of measurements of a set of accurately known delays is required.
>> Useful results can be produced by measuring the delay between various outputs of a shift register clocked at a sequence of different measured frequencies.
>>      
>>> I was thinking that would be nice to try to
>>> feed it with signals similar to the real ones,
>>> but that can be controlled: PPS + 10MHz reference,
>>> without the PPS tipical jitter.
>>>
>>>        
>> One should characterise the interpolator linearity etc first.
>>      
>>> To do so I was thinking to use the PPS from
>>> one of the 2 FE5680 and the 10MHz from the
>>> second ad use these to simulate the real signals.
>>>
>>> I can tune the frequency of the Rb with the
>>> serial interface (tested and working).
>>> I'd like to verify both the resolution and
>>> repeteability.
>>>
>>> I was trying to figure the approx jitter
>>> I will have using the Rb like I said above,
>>> so I'm giving an eye to this diagram from
>>> John Miles page: http://www.ke5fx.com/rb.htm
>>>
>>> If I'm understanding correctly, that 5680
>>> at 1s should have most of the jitter (95% +-2sigma)
>>> into an interval +- 3.08x10^-11 wide, i.e. about 62pS
>>> on the PPS signal (non considering the PPS buffer
>>> inside the 5680). Is this how it work, or I'm mistaking?
>>> This is from only one unit, but both unit will have
>>> the jitter, how to take into account the jitter
>>> from both?
>>>
>>> Is there a better method to make this test?
>>> I could try to test the TAC alone feeding it
>>> with a 100 to 200nS pulse, but I dont know
>>> from where to start to generate a clean stable
>>> and repeteable pulse.
>>>
>>>        
>> You dont need one (see above) as long as you have the means to accumulate the results of 100,000 measurements or preferably more.
>>      
>>> I have the 2 5680, the counter with it's 10MHz
>>> inputs and outpus, and a Vectron OCXO that came
>>> with one of the 5680, with these markings:
>>> OCXO500-18 63.897600MHz
>>> 34537 A0715
>>> and...
>>> soldering iron, solder and scrap electronics :)
>>>
>>> Thanks,
>>> Fabio.
>>>
>>>        
>> Bruce
>>
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>
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