[time-nuts] disciplining sound card

Azelio Boriani azelio.boriani at screen.it
Fri Jul 6 18:50:20 UTC 2012


What if I post a schematic with a Lattice M4-64/32 CPLD? If you can program
this CPLD I can send the .JED file, the schematic...

On Fri, Jul 6, 2012 at 7:07 PM, Bill Dailey <docdailey at gmail.com> wrote:

> Yes,  that i know.  Just don't have the wherewithal to implement that
> myself.
>
> ----------------
> The integer greatest common divisor 10MHz/25.576MHz is 16KHz so a simple
> PLL should go through that frequency.
>
> Sent from my iPhone
>
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