[time-nuts] disciplining sound card

Azelio Boriani azelio.boriani at screen.it
Sun Jul 8 11:59:09 UTC 2012


Here the modified VHDL with the 48KHz and 96KHz clock out:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY FRSync IS
PORT (ClkIN, RefIN: IN std_logic; -- ClkIN is 24.576MHz/1536->16KHz, RefIN
is 10MHz/625->16KHz
PWMOut, F48KHz, F96KHz: OUT std_logic);
END ENTITY FRSync;
ARCHITECTURE Proc4 OF FRsync IS
SIGNAL Cnt5A: std_logic_vector (2 downto 0);
SIGNAL Cnt125 std_logic_vector (6 downto 0);
SIGNAL Cnt768 std_logic_vector (9 downto 0);
SIGNAL Cnt2, Cnt5B, Cnt125N, Fr625: std_logic;
BEGIN
-- Dividers section
Div125: PROCESS -- Divide the 10MHz first by 125 then by 5
BEGIN
WAIT UNTIL RefIN'EVENT AND RefIN='1';
IF Cnt125="1111100" THEN
Cnt125<= (OTHERS=> '0');
ELSE
Cnt125<= Cnt125+1;
END IF;
END PROCESS Div125;
Div5A: PROCESS
BEGIN
WAIT UNTIL Cnt125(6)'EVENT AND Cnt125(6)='1';
IF Cnt5A="100" THEN
Cnt5A<= (OTHERS=> '0');
ELSE
Cnt5A<= Cnt5A+1;
END IF;
END PROCESS Div5A;
Div5B: PROCESS
BEGIN
WAIT UNTIL Cnt125N'EVENT AND Cnt125N='1';
Cnt5B<= Cnt5A(1);
END PROCESS Div5B;
Div512: PROCESS -- Divide the 24.576MHz first by 512
BEGIN
WAIT UNTIL ClkIN'EVENT AND ClkIN='1';
Cnt512<= Cnt512+1;
END PROCESS Div512;
Div3A: PROCESS -- Divide by 3 50% duty
BEGIN
WAIT UNTIL Cnt512(8)'EVENT AND Cnt512(8)='1';
IF Cnt3A="10" THEN
Cnt3A<= (OTHERS=> '0');
ELSE
Cnt3A<= Cnt3A+1;
END IF;
END PROCESS Div3A;
Div3B: PROCESS
BEGIN
WAIT UNTIL Cnt512N'EVENT AND Cnt512N='1';
Cnt3B<= Cnt3A(0);
END PROCESS Div3B;
-- Combinational section
Cnt125N<= NOT Cnt125(6);
Cnt512N<= NOT Cnt512(8);
Fc3<= '1' WHEN Div3A (0)='1' OR Div3B='1' ELSE '0'; -- 50% divide-by-3
Fr625<= '1' WHEN Div5A (1)='1' OR Div5B='1' ELSE '0'; -- 50% divide-by-5
PWMOut<= Fr625 XOR Fc3; -- The XOR needs exactly a 50% duty cycle
F48KHz<= Cnt512(8);
F96KHz<= Cnt512(7);
END ARCHITECTURE Proc4;

On Sun, Jul 8, 2012 at 7:34 AM, Demian Martin <demianm_1 at yahoo.com> wrote:

> We need a better idea what the goal is. If it's to sample and digitize data
> at a specific time you may need to "roll your own" but if it's to figure
> out
> the time of an event or to look at spectral info a mid price premium
> soundcard like the Juli@ should be more than adequate. Knowing when in a
> sample cycle the actual sample was taken may not have a lot of meaning
> since
> the incoming info is bandlimited. The standard sample rates, 44.1, 48,
> 88.2,
> 96, 176.4 and 192 KHz have roots in the video world and are not nice
> numbers
> per 10 MHz references.  Audio cards use either a single 24.576 MHz crystal
> and PLL to generate the other frequencies or both a 24.576 MHz and a
> 22.5792
> MHz crystal. The ones with separate crystals do have less jitter.
>
> Word clock can only be used with difficulty if the card was not designed
> for
> it. You cannot force word clock and have the rest of the I2C buss work
> right. You can lock to an external SPDIF or AES signal (they are virtually
> the same except for some info bits and the signal levels. AES is 4V P-P
> differential into 110 Ohms. SPDIF is 1V P-P into 75 Ohms (an AES variant is
> the same). The same receivers are used for both.
>
> If absolute timing is important you can easily use an external capture
> device (TI, ADI and AKM all have very good demo boards) that you can clock.
> Clocking at 10 MHz will work in some systems on the external spdif input
> but
> many will reject it since it's too far from an accepted frequency. The high
> end cards that might will resample everything messing with your carefully
> captured data. If you do get the data in the existing software will give
> you
> confusing results. There may be a simple way to add a SMPTE time code to
> the
> data as its captured. It's done in the video industry.
>
> If you don't want a delta sigma ADC you can substitute a different kind but
> there will be tradeouts. Usually bit depth vs sample rate vs. accuracy.
>
> A simple way to discipline a 22.5792 and a 24.576 VCXO to a 10 MHz
> reference
> would be very interesting.
>
> A good way to verify the performance and any issues with a capture system
> would be to make a count down from the 10 MHz to an audio frequency and
> capture it. Do a really deep fft and look for stuff that should not be
> there
> (anything but the countdown).
>            Demian Martin
>
>
>
> _______________________________________________
> time-nuts mailing list -- time-nuts at febo.com
> To unsubscribe, go to
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
> and follow the instructions there.
>


More information about the time-nuts mailing list