[time-nuts] GPSDO control loops and correcting quantizationerror

Poul-Henning Kamp phk at phk.freebsd.dk
Sat Sep 15 07:36:54 UTC 2012


I did some experiments with a charge-transfer D/A and at least as far
as I can see, that has the potential to go beyond 30 bits.

The key observation is, as others have pointed out, that we only really
care about relative local linearity, the PLL loop will take care of
everything else.

What I did was take a large-ish low-leakage capacitor and put a voltage
follower after it, to drive the EFC pin.

The PLL loop, implemented in software, controlled two fet-switches
which would deliver positive or negative pulses to the capacitor
through matched resistors.

The software involvement allows for trivial calibration of any
unbalance between the switches & resistors, and even, if you manage
to measure and model it, I didn't, the capacitors leakage current.

By controlling the length of the pulses, you can get incredibly small
"steps" in your output voltage while retaining a wide dynamic range.

The neat thing is that you do not need a particularly precise or stable
reference voltage for this design.

Ideally you would want to drive the switches with constant current
sources, but if you put an 10bit ADC on the voltage followers output,
so you know the approximate voltage over the capacitor, it is trivial
to model the charge delivered per unit time in software.

At the time I had not read the HPJ article about the 3458A, and if
I do it again, there are several tricks from there I would employ:
Balanced pulses to linearize switch-noise and multiple drivers of
different strengths for faster capture.

-- 
Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG         | TCP/IP since RFC 956
FreeBSD committer       | BSD since 4.3-tahoe    
Never attribute to malice what can adequately be explained by incompetence.



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