[time-nuts] Trimble Resolution SMT GG weirdness

[Jim Lux]

On 4/22/13 3:15 PM, Hal Murray wrote:
>
> dginsburg at gmail.com said:
>> First, the frequency offset of the microcontroller. I use a built-in
>> counting timer in the uC which runs at 84MHz to measure the duration between
>> 2 PPS. What I get is ~84008000 timer ticks between two pulses, which
>> corresponds to about 95ppm offset. While the crystal on the board is of the
>> cheapest variety, I think 95ppm is just too much. Is that correct, and 95ppm
>> offset even for a the most crappy oscillator is not a reasonable value?
>
> It isn't totally unreasonable.
>
> Yes, 95 PPM is the high end of even cheap crystals, but it could easily be a
> design error.  The capacitive loading of the circuit might not match the
> specs on the crystal.
>
> There is also the possibility of a software bug.  OSes have a long history of
> not getting that quite right.  They are usually close enough so that nobody
> cares unless some geek starts monitoring the details.
>


Assuming the software is reading some hardware counter when it gets the 
pulse, there could be variable latency in the routine.  8000 ticks is a 
lot of instructions though..

If you read, say, 100 intervals, what does the distribution look like?
is it always the same number (crystal is too high in frequency), or does 
it vary (software might be an issue)