[time-nuts] frequency multiplication

[Bob Camp]

Hi

A discrete VCXO and PLL chip will always outperform the "buit in VCO" silicon parts. The CY2302 is quite noisy even by silicon standards. Your doubler / tripler will give you good close in noise, but poor performance broadband. A lot depends on what the ultimate use for the DDS output is. The DDS it's self likely has enough issues noise and spur wise to make the quality of the clock driving it somewhat less important. 

Bob

On Aug 30, 2013, at 12:56 PM, "Collins, Graham" <CollinG at navcanada.ca> wrote:

> 
> 
> Good day all,
> 
> Lately I have been contemplating a variety of methods to take a high stability 10 MHz reference multiply it up to a suitable frequency for use a the reference clock for a DDS, for example 10 MHz to 80 MHz or 120 MHz (or whatever).
> 
> On method is to use simple diode based doublers and triplers to get to where I want to be, that 10 x 2 x 2 x 2 = 80 or 10 x 3 x 2 x 2 = 120 or whatever combinations that would accomplish the same thing.
> 
> Another is the use of something like the Cypress CY2302 frequency multiplier and zero delay buffer which uses a PLL to perform it's magic (i.e 2 or 4 or 8 or 16 times multiplication).
> 
> My goal is to be able to use the DDS to generate a stable frequency close to the stability of the 10 MHz reference with good phase noise although the latter criteria is ill defined and of lesser importance than frequency stability at the moment.
> 
> Anyone have any firsthand experience with the likes of the CY2302 and can comment on their suitability for this task?
> 
> Cheers, Graham ve3gtc
> 
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