[time-nuts] GPSDO PLL convergence question

[Bob Camp]

Hi

Convergence in a PLL has no absolute definition. In some cases 45 degree phase error = all is running fine. 

I would simply track GPS time vs OCXO time and declare it ok when it's inside some magic number of nanoseconds. 

Bob

On Aug 30, 2013, at 7:08 PM, Bob Stewart <bob at evoria.net> wrote:

> I finally (think I) understand enough about my hardware and the data that my PLL is working!  Now for the hard part: When do I decide it's converged?  I believe that the maximum time in seconds till convergence is on the order of:
> 
> (OCXO range / DAC range) / (error count *  DAC volts per step) 
> 
> where:
> "OCXO range":  the tuning range of the OCXO in Hz - let's use 8 Hz
> "DAC range" is the voltage range of the DAC from bottom to top - let's use 6 V
> "error count": the number of DAC steps till convergence
> "DAC volts per step": voltage change for one step of the DAC - let's use .0003 volts per step
> 
> For example, discounting the UT+ sawtooth and OCXO stability, the last 1 step of the DAC until complete convergence could take up to:  (6/8) / (1 * .0003) ~ = 2500 seconds until convergence.  Two steps away would be ~1250, three steps ~833, etc.
> 
> So my dilemma is to pick a number when it's safe to say that the PLL is converged.  Do I just wait until there is 2500 seconds between DAC changes or do I pick a lower number?  And, conversely, when I do say it's no longer converged?  Or have I just got it all wrong?  (Apologies if I've gotten terminology wrong.)
> 
> The methodology is similar to a Bang-Bang PLL.  I keep a running track 
> of the OCXO error count per 1PPS, and if it over-counts twice, the DAC is 
> reduced one step, and if it under-counts twice then the DAC is 
> increased.  Any 1PPS where the count is correct is thrown out.  The name
> "Bang-Bang PLL" doesn't seem appropriate, so I think this should be 
> called a "Tick-Tock PLL".  =)
> 
> Bob - AE6RV
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