[time-nuts] sysclock source for AD9912 DDS?

Anders Wallin anders.e.e.wallin at gmail.com
Tue Dec 31 11:07:55 EST 2013


Some more testing today. It turns out that AD's schematic for the
evaluation board doesn't match with reality - and so I had not connected
the PLL filter components at all previously! Now they are 'in the loop' and
I get reasonable results without the 2x reference clock setting. With 2x
activated there are still very strong spurs. I have updated my blog with
pictures from today:
http://www.anderswallin.net/2013/12/ad9912-dds-test/

Could the remaining -60 dBc spurs at +/- 50 kHz be due to my 10MHz clock
source, an Agilent 33120A?

Next I will try cooking up some Arduino code for controlling the DDS over
3-wire bit-banged SPI (hardware SPI port is already in use on my arduino).

Anders


On Mon, Dec 30, 2013 at 5:56 PM, Anders Wallin
<anders.e.e.wallin at gmail.com>wrote:

> I've tested the AD9912 evaluation board:
>
> http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png
>
> I want to use it with a 10MHz external input clock, but it looks like the
> on-board PLL that generates a 1200MHz sample clock from my input isn't that
> great, since I get strong side-bands on the output that are only 18-20 dB
> down from the fundamental.
>
> So it looks like I need to supply a clean 800-1000MHz clock to the DDS to
> get a clean output. Any ideas/suggestions for generating this from a 10 MHz
> sine?
> Driving the DDS system clock from an expensive RF generator (e.g. HP
> 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable
> simply/cheaply.
>
> Anders
>


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