[time-nuts] An embedded NTP server

[Bob Camp]

Hi

The only problem you may run into with an input capture is that the 72 MHz may be from an internal VCO that's locked to the external clock source or crystal. Often these micro's don't have VCO's that are as good a one might hope. You will indeed have less than 1 UI jitter, you may not have a whole lot less…

Bob

On Dec 31, 2012, at 10:56 PM, Michael Tharp <gxti at partiallystapled.com> wrote:

> On 12/28/2012 12:34 PM, Chris Albertson wrote:
>> One idea that I like is to first get a large FPGA.  Then you load in a
>> "soft CPU" and then you run an OS and NTP on the soft CPU.   Inside
>> the softCPU the counter is implemented like it is in a real CPU but
>> you can add the ability for a PPS to "latch" it.  Basicaly you move
>> the interrupt handler to hardware.     The trick is if you can get
>> good enough performance out of the soft CPU?    There is some
>> intelectual property problems with some soft CPS but I'm pretty sure
>> there are free SPARC CPS you can use and SPARC is ideal for this as it
>> can run BSD Unix.
> 
> Most microcontrollers that I have seen (PIC, ARM, presumably AVR as well) already have a peripheral called "input capture" that does exactly this, and that's what my project is using. Since it's part of the timer peripheral it usually runs at (up to) the same speed as the CPU which in my case is 72MHz, plenty for a decent lock. It simply grabs the current value of the counter when a pulse arrives and saves it until the CPU can get around to retrieving it. To get another order of magnitude the next step would be an analog TDC or a FPGA running a vernier TDC, but you can get quite satisfactory results with just an off-the-shelf microcontroller.
> 
> Free CPU cores for FPGAs are not a problem, I have investigated a little and come up with a few candidates. Right now my favorite would be a microblaze clone called aemb, but there is also light8080 (tiny but 8-bit is a headache) and OpenRISC (fat but full-featured). There is a free vernier TDC core as well that is made available by CERN. They are using it in their White Rabbit system which does some rather neat things with custom Ethernet transceivers and switches that can distribute time across significant lengths of fiber to very good precision. I have not yet dedicated enough time to finish wiring the TDC to a CPU but I have made some progress; it synthesizes but is not yet operating correctly. I will be the first to admit I am not very experienced with FPGAs but given enough time and interest it can be made to work.
> 
> -- m. tharp
> 
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