[time-nuts] Riley paper on Tight Phase Lock Loop

WarrenS warrensjmail-one at yahoo.com
Wed Jan 30 19:51:28 EST 2013


>It would be nice if a real schematic and BOM was posted. it's like a big 
>mystery ...
> /tvb

As Adrian and Bob pointed out, W. J. Riley's site has all the information 
needed to make the higher cost TPLL version he did including his PCBs.

The bigger mystery seems to be how easy a TPLL can be built without loosing 
performance.
One version of the TPLL tester only needs 8 circuit parts plus + Power 
supplies etc,
These are all clearly specified on the bottom block diagram, dated June 7, 
2010 at
http://www.ke5fx.com/tpll.htm
And even that complete working, simple version, is good enough that the 
performance is still mostly limited by the HP10811 Reference Osc and not the 
TPLL circuit.

BOM for "Extra simple TPLL"
Nothing is critical, performance is determined by the Ref Osc.
1) Phase detector  =  SYPD-1
2) 100KHz  LPF = two each 220 ohm in series and two 0.0047uf caps to gnd
3) Amp = OP-27 Pin 3 is input, pin 6 is output
4) Amp feedback gain = + 300 set using a 30K feedback and 100 Ohm resistor 
to gnd
5) 20 Hz LPF =  8K ohm series R and 1uf to gnd
6) Ref Osc = HP10811
7) A slow mv DVM and/or a 16 bit ADC sampling at 100Hz or more.
8) misc connectors, PS, S/W, etc.

The configuration of the TPLL 1.0 that John tested, uses a 3dB and 5dB pad 
for isolation, (no real need for Osc buffers),
and has a higher closed loop PLL bandwidth using an op37 with more gain, (a 
tighter TPLL)
This can be seen by clicking on the underlined "Here" of John's report next 
to Fig 1.7 at
"Warren's annotated block diagram can be seen HERE."

ws

****************************
Hi Tom,

Bill has actually published detailed schematics etc here:
http://www.stable32.com/A%2010%20MHz%20OCVCXO%20and%20PLL%20Module.pdf

Btw. what do you think about his small DMTD system?
http://www.wriley.com/A%20Small%20DMTD%20System.pdf

Adrian

*******************
Tom Van Baak schrieb:
> Hi Bob,
>
> The TPLL method is described by NIST: 
> http://tf.nist.gov/phase/Properties/one.htm
>
> A few years ago it was re-developed by WarrenS, a dedicated and frequent 
> contributor to this list.
>
> See also John Miles excellent report: http://www.ke5fx.com/tpll.htm
> Or if that's dead, see 
> http://web.archive.org/web/*/http://www.ke5fx.com/tpll.htm
>
> It's nice that W.J. Riley also tried it. If you know Bill, he makes us all 
> look like amateurs.
>
> We know cases where TPLL works quite well; there are other cases where it 
> doesn't. It would be nice if either Warren or John or Bill or anyone else 
> posted a real schematic and BOM so that others could reliably duplicate, 
> corroborate, refute, or refine their results. For some reason, it's like a 
> big mystery; very unlike what we try to foster here on time-nuts: the free 
> sharing of information, methods, experience, designs, results, and 
> conclusions.
>
> /tvb
>*****************************
> ----- Original Message -----
> From: "Robert Darby" <bobdarby at triad.rr.com>
> To: <time-nuts at febo.com>
> Sent: Wednesday, January 30, 2013 10:32 AM
> Subject: [time-nuts] Riley paper on Tight Phase Lock Loop
>
>> Gentlemen,
>>
>> I've been a lurker on this list since early in 2012.  I do not possess a
>> technical background but do have some interest in time measurement 
>> topics.
>>
>> I was reading some of W. J. Riley's papers and saw that after the long
>> and contentious discussion on this list Mr Riley built and tested a
>> tight phase lock loop system.
>>
>> I have failed to turn up any mention of his paper on this list and was
>> curious if anyone has read it or perhaps duplicated it?
>>
>> He writes "HP 10811 ovenized  crystal oscillators are used as both the
>> locked oscillator and PLL reference, and the system thus measures the
>> combined instability of two presumed identical and uncorrelated
>> devices." He further notes that "These results agree well with other
>> measurements  for  this type of crystal oscillator."
>>
>> The paper is found at:
>>
>> http://www.stable32.com/Frequency%20Stability%20Measurements%20Using%20a%20Tight%20Phase%20Lock%20Loop.pdf
>>
>> The construction is described in greater detail in a separate paper:
>>
>> http://www.stable32.com/A%2010%20MHz%20OCVCXO%20and%20PLL%20Module.pdf
>>
>> The OCVCXO and PLL Board described therein appears to be a very
>> versatile piece of gear for anyone using 10811's.   Riley gives an
>> example using the module to clean-up the output of a LPRO-101 rubidium
>> (page 9).
>>
>>
>> Regards,
>> Bob Darby
>>
> 



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