[time-nuts] Brooks Shera

David McGaw n1hac at alum.dartmouth.org
Mon Mar 25 14:03:23 EDT 2013

Actually, most modern FFs are hardened against metastability so often a 
single synchronizer will do especially if it is feeding a synchronous 


On 3/25/13 1:56 PM, Attila Kinali wrote:
> On Mon, 25 Mar 2013 06:56:30 -0700
> "Tom Van Baak" <tvb at LeapSecond.com> wrote:
>>> I think with these it becomes obvious where the problem lies and what
>>> the solution is.
>> I realize there are many cases where clock domain considerations are
>> important. But why does it matter in a device that is simply doing
>> long-term 1PPS statistical sampling?
>> Could one of you clock domain specialists actually spell out the
>> GPSDO problem for the rest of us, nanosecond-by-nanosecond?
> I'm by far not an expert, but i try to explain it anyways:
> The PPS sampling is exactly the problem here.
> The PPS occurs at any given time relative to the 24MHz clock. This means
> setup and hold times can be violated in a synchronous circuit.
> In this case, the input to the 75HCT4520 is an AND connection of the 24MHz
> clock and the PPS. Due to this, the clock input to the counter in the
> 74HCT4520 can become very short, short enough that the minimum width of
> the clock pulse is violated (>15ns). Because of this, the behaviour of the
> counter is undefined and can lead not only to missing one count (which
> would be caught by the PI control loop as additional noise), but the output
> of the D-flip flops in the counter can switch or not switch depending
> on the wheather in Guatemala. Ie the output of the counter becomes
> (more or less) random. Which in turn means the lower 4 bit of the
> input to the PI control loop are wrong[1]. Or in terms of time, we
> might be off by +/-2^4*42ns=672ns, which is a major hit against the
> PI loop (like knocking it with a sledge hammer).
> Additionally, it is known that logic circuits can be caught nearly
> indefinitly in a meta stable state (until the next clock pulse),
> if the circuit has no provisions for this. Ie the output of the
> flip flops would not be 1 or 0, but something inbetween, with some
> negative effects on the circuitry downstream.
> 			Attila Kinali
> [1] I ignore the additional +/-1 of bit 5 for clarity

More information about the time-nuts mailing list