[time-nuts] Metastability (was Brooks Shera)

lists at lazygranch.com lists at lazygranch.com
Mon Mar 25 18:51:07 EDT 2013


There is an AMD patent where they actually drive the input pin to make it decide rather than hang. I have no first hand knowledge with the design (well other than knowing the designer) since I couldn't use the scheme in my own designs.

-----Original Message-----
From: Bob Camp <lists at rtty.us>
Sender: time-nuts-bounces at febo.com
Date: Mon, 25 Mar 2013 18:02:33 
To: Discussion of precise time and frequency measurement<time-nuts at febo.com>
Reply-To: Discussion of precise time and frequency measurement
	<time-nuts at febo.com>
Subject: Re: [time-nuts] Metastability (was Brooks Shera)

Hi

In normal operation, the counter is clocking back and forth across the 1024 / 24,000,000 boundary. It has to do this for the control loop to "see" anything. Put another way, if it's always 1024 / 24,000,000 the loop does nothing at all. 

It's the "race" between things like enable and clock or data and clock that generates metastable conditions. If the data is changing as the clock fires, the flip flop oscillates rather than goes to a single state. In this case oscillation is not a good thing…..

Bob

On Mar 25, 2013, at 5:43 PM, Chris Albertson <albertson.chris at gmail.com> wrote:

> First off we have the answer.  This thing works very reliably well.
> The question is "why?"
> 
> In the normal steady state case the phase of the VCXO is held to be
> 1024/24,000,000 seconds.  This means the plus from pin 15 of the 4046
> would be about 4,000 nanoseconds long and would never be anything so
> much as a factor of ten away from 4 uSec.
> 
> One thing I notice is that I think the QST artcle has the pins on the
> 4520 mislabeled.  Pins 9 and 10 are the two inputs to an AND gate.
> The 24MHz counter is being "anded" with the phase detector and the
> result of the AND is then fed to the counter.  My data sheet shows
> pins 2 and 10 as being called "enable".  So what we have as a pulse
> that is about 4uSec wide gating a 24MHz square wave.
> 
> There might be a "race" to see if the enable pin or the clock pin gets
> a pulse first and it would be a coin flip now and then but it's only
> an off by one problem.
> 
> In the no-steady state case, when power is first applied before the
> loop is closed.  I don't think we care about glitches and and if the
> VXCO is stable but as soon as it does locj the pulse going to pin the
> 4520's pin-10 will be 1024 times longer than the the period of the
> signal at pin-9  Again, pins 10 and 9 are the two inputs to an AND
> gate (after pin-10 is inverted)
> 
> On Mon, Mar 25, 2013 at 2:04 PM, Bob Camp <lists at rtty.us> wrote:
>> Hi
>> 
>> With the 24 MHz clock in the circuit, and the logic families shown, the most
>> likely metastability issues are edge rather than clock pulse width related.
>> When you hit the "magic window" (think picoseconds) there is a probability
>> of going metastable. It's not a 100% thing. Even with multiple synchronizer
>> stages *not* being metastable is also not a 100% guarantee.
>> 
>> The real question is - does a once every X seconds / hours / centuries event
>> bother me in the application? Once you get to a multi stage synchronizer,
>> the dimensions on the time are large enough that the answer is generally no.
>> The event is so rare that you will never see it with these data rates. Being
>> sure it's fixed is easy.
>> 
>> It's the flip side - error rate without the synchronizer that is a bit
>> harder to quantify. Things could run for weeks outside the threat window. Is
>> it a several times a minute (every few days) or once an hour (every few
>> weeks) problem? In the first case, you probably do care. Multiple hits per
>> minute will mess up the loop. In the second case, you will never notice the
>> issue.
>> 
>> Of course, boost the clock, change the logic family, mix logic families,
>> fiddle this or that and you probably should look at things again...
>> 
>> Bob
>> 
>> -----Original Message-----
>> From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com] On
>> Behalf Of Bruce Griffiths
>> Sent: Monday, March 25, 2013 4:38 PM
>> To: Discussion of precise time and frequency measurement
>> Subject: Re: [time-nuts] Metastability (was Brooks Shera)
>> 
>> Both edges of the 24MHz clock gating pulse are asynchronous with respect
>> to the signal being gated.
>> Metastability can result with clock pulse widths that lie within a
>> critical range.
>> 
>> Bruce
>> 
>> Chris Albertson wrote:
>>> On Mon, Mar 25, 2013 at 12:45 PM, David McGaw<n1hac at alum.dartmouth.org>
>> wrote:
>>> 
>>>> S/LS logic was introduced in the mid 70's, F/AS/ALS around 1980, HC was
>>>> early 80's.  By the third 7400 generation (F/AS/ALS) the problem was well
>>>> known with parameters available and the logic fairly hard to it
>>>> 
>>> I think this is all moot because as I just wrote in another email the
>>> PPS signal never gets out of the 74hct4046 chip.   What gets out is
>>> the output of  "Phase Detector #3".  You've have to know in some
>>> detail how the 4046 chips' PD3 works.
>>> 
>>> Chris Albertson
>>> Redondo Beach, California
>>> _______________________________________________
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>>> 
>>> 
>> 
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> 
> 
> 
> -- 
> 
> Chris Albertson
> Redondo Beach, California
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