[time-nuts] 74HCT9046A Max. Operating Frequency

[sg sg]

Thanks very much for your responses!

> For 24.576 MHz VCXO, the fractional change in frequency will be in multiple
> ppm not octaves, and I would naturally gravitate towards a simple diode DBM.

To avoid lock issues I'd still want a phase-frequency detector; the PLL bandwidth in my case is very low (a few Hz), which makes the lock range tiny if a "phase only" detector is used (I've run into this recently with some other project).

> 24,576 MHz is 128x192 kHz which makes essentially any divide by 2^N chip
> capable of the frequency a target. Is your reference signal also 24,576
> MHz or some other frequency?

The source is an AK4114 AES/EBU audio receiver, which has both master clock (24.576 MHz) and "word select" rate (48-192 kHz) outputs. Perhaps it is better to run the PLL at the latter? Any disadvantages from this?

Regards,
Samuel