[time-nuts] Homebrew frequency counter, need help

Li Ang lllaaa at gmail.com
Mon Dec 1 11:39:57 EST 2014


New tests today. It's strange that the data is not so stable as before.

I've already add a 22uF Ceramic Cap and a 100nF. 10ohm resistor is removed.




First:
reg [15:0] shift;
always @(posedge refclk10M) begin
shift <= {shift[14:0], sw_gate};
end
assign tdc_start = shift[3];
assign tdc_stop1 = shift[4];
assign tdc_stop2 = shift[5];

stop1-start=  935, stop2-stop1= 1049
stop1-start=  957, stop2-stop1= 1047
stop1-start=  961, stop2-stop1= 1046
stop1-start= 1005, stop2-stop1= 1049
stop1-start=  930, stop2-stop1= 1048
stop1-start=  911, stop2-stop1= 1046
stop1-start= 1005, stop2-stop1= 1049
stop1-start=  936, stop2-stop1= 1048
stop1-start=  930, stop2-stop1= 1047
stop1-start= 1006, stop2-stop1= 1048
stop1-start=  955, stop2-stop1= 1047
stop1-start=  976, stop2-stop1= 1047
stop1-start=  932, stop2-stop1= 1047
stop1-start=  965, stop2-stop1= 1048
stop1-start=  913, stop2-stop1= 1048
stop1-start=  955, stop2-stop1= 1048
stop1-start=  953, stop2-stop1= 1049
stop1-start=  993, stop2-stop1= 1049
stop1-start=  993, stop2-stop1= 1049
stop1-start=  982, stop2-stop1= 1048
stop1-start=  918, stop2-stop1= 1047
stop1-start=  961, stop2-stop1= 1046
stop1-start= 1007, stop2-stop1= 1047
stop1-start=  912, stop2-stop1= 1046
stop1-start=  928, stop2-stop1= 1049
stop1-start=  995, stop2-stop1= 1048
stop1-start= 1003, stop2-stop1= 1047
stop1-start=  966, stop2-stop1= 1046
stop1-start=  953, stop2-stop1= 1050
stop1-start=  971, stop2-stop1= 1047
stop1-start=  995, stop2-stop1= 1045
stop1-start=  959, stop2-stop1= 1048
stop1-start=  914, stop2-stop1= 1047
stop1-start= 1002, stop2-stop1= 1047
stop1-start= 1004, stop2-stop1= 1047


=========================================
Second:
assign tdc_start = shift[3];
assign tdc_stop1 = shift[5];
assign tdc_stop2 = shift[7];

//stop2-stop1 is not exact 2 times as test 1.
stop1-start= 2024, stop2-stop1= 2104
stop1-start= 2034, stop2-stop1= 2106
stop1-start= 1991, stop2-stop1= 2104
stop1-start= 2016, stop2-stop1= 2105
stop1-start= 2019, stop2-stop1= 2105
stop1-start= 2005, stop2-stop1= 2106
stop1-start= 2006, stop2-stop1= 2104
stop1-start= 1962, stop2-stop1= 2104
stop1-start= 2056, stop2-stop1= 2106
stop1-start= 2020, stop2-stop1= 2105
stop1-start= 1961, stop2-stop1= 2107
stop1-start= 2011, stop2-stop1= 2105
stop1-start= 2005, stop2-stop1= 2106
stop1-start= 2035, stop2-stop1= 2106
stop1-start= 2011, stop2-stop1= 2105
stop1-start= 2006, stop2-stop1= 2104
stop1-start= 2013, stop2-stop1= 2104
stop1-start= 1964, stop2-stop1= 2104
stop1-start= 2054, stop2-stop1= 2105
stop1-start= 2056, stop2-stop1= 2106
stop1-start= 2019, stop2-stop1= 2106
stop1-start= 1982, stop2-stop1= 2105
stop1-start= 2010, stop2-stop1= 2105
stop1-start= 1964, stop2-stop1= 2106
stop1-start= 1989, stop2-stop1= 2106
stop1-start= 2008, stop2-stop1= 2107
stop1-start= 2059, stop2-stop1= 2106
stop1-start= 1985, stop2-stop1= 2104
stop1-start= 2011, stop2-stop1= 2105
stop1-start= 1962, stop2-stop1= 2105
stop1-start= 2012, stop2-stop1= 2104
stop1-start= 2008, stop2-stop1= 2105
stop1-start= 2048, stop2-stop1= 2104
stop1-start= 2009, stop2-stop1= 2106
stop1-start= 2009, stop2-stop1= 2105
stop1-start= 2006, stop2-stop1= 2105
stop1-start= 2009, stop2-stop1= 2105
stop1-start= 2009, stop2-stop1= 2104
stop1-start= 2005, stop2-stop1= 2105
stop1-start= 2049, stop2-stop1= 2105
stop1-start= 2023, stop2-stop1= 2106

++++++++++++++++++++++++++++++++++++++++++++++++++
Third:
//This test shows that stop2 path is shorter than stop1 path. I need to
consider it when doing the calc.
assign tdc_start = shift[3];
assign tdc_stop1 = shift[5];
assign tdc_stop2 = shift[5];

stop1-start= 2059, stop2-stop1=   -5
stop1-start= 2065, stop2-stop1=   -6
stop1-start= 1989, stop2-stop1=   -2
stop1-start= 2013, stop2-stop1=   -2
stop1-start= 2011, stop2-stop1=   -5
stop1-start= 2019, stop2-stop1=   -6
stop1-start= 1987, stop2-stop1=   -6
stop1-start= 2065, stop2-stop1=   -2
stop1-start= 1974, stop2-stop1=   -6
stop1-start= 1968, stop2-stop1=   -2
stop1-start= 2055, stop2-stop1=   -5
stop1-start= 2065, stop2-stop1=   -5
stop1-start= 2012, stop2-stop1=   -2
stop1-start= 2035, stop2-stop1=   -2
stop1-start= 2014, stop2-stop1=   -2
stop1-start= 2014, stop2-stop1=   -6
stop1-start= 2028, stop2-stop1=   -1
stop1-start= 2034, stop2-stop1=   -6
stop1-start= 2013, stop2-stop1=   -2
stop1-start= 1974, stop2-stop1=   -5
stop1-start= 2014, stop2-stop1=   -2
stop1-start= 2009, stop2-stop1=   -1
stop1-start= 2029, stop2-stop1=   -5
stop1-start= 2053, stop2-stop1=   -2
stop1-start= 2017, stop2-stop1=   -5
stop1-start= 2013, stop2-stop1=   -2
stop1-start= 1992, stop2-stop1=   -1
stop1-start= 2016, stop2-stop1=   -2
stop1-start= 1970, stop2-stop1=   -2
stop1-start= 1973, stop2-stop1=   -2
stop1-start= 2065, stop2-stop1=   -5
stop1-start= 1975, stop2-stop1=   -5
stop1-start= 2017, stop2-stop1=   -6
stop1-start= 2013, stop2-stop1=   -6
stop1-start= 2016, stop2-stop1=   -2
stop1-start= 1987, stop2-stop1=   -2
stop1-start= 2062, stop2-stop1=   -6
stop1-start= 2021, stop2-stop1=   -5




2014-11-29 1:41 GMT+08:00 Bob Camp <kb8tq at n1k.org>:

> Hi
>
> > On Nov 28, 2014, at 10:14 AM, Li Ang <lllaaa at gmail.com> wrote:
> >
> >>
> >> 1) What frequency is the crystal at? (can you drive the chip from an
> OCXO?)
> >
> > I'm clking this chip with the refclk/2=5Mhz, which is done by cpld.
> > something like always @(posedge refclk) tdc_clk <= ~tdc_clk; Not sure if
> > it's noisy.
>
> If the clock source into the CPLD is clean, the output should not be to
> bad.
>
> >
> > 2) Is there more bypassing on the circuit than shown? (If not, add some
> >> more).
> >
> > Since there is only few power supply pins, I just put 100uF + 100nF
> there.
> > I can try put more to see if helps. And I'm going to use dedicated LDO
> for
> > digital part and analog part next time to make a new pcb.
>
> I suspect that a few more 100nF caps might be a good idea. They may not
> help, but it would rule out the supply as an issue.
>
> >
> > 3) How confident are you of your input signal? (can you check it with a
> >> “known good” counter?)
> >
> > The best counter I get is the RACAL DANA 1992. That is not good enough.
> I
> > think the accurarcy is not a problem, as if the reference is good enough,
>
> That’s correct. I was hoping you might be able to borrow a SR620 or 53132
> for a few minutes to check your input signal.
>
> > it's only the matter of math. I prefer to enhance the resolution and
> reduce
> > noise.
>
> If the noise is on your test signal, it can be very frustrating to chase
> it with a lot of software work.
>
> > I'm using Trimble GPSDO(NTPX26AB) as the signal source
>
> The GPSDO should be fairly quiet, but it has an ADEV that’s a bit high.
> The outputs also can have noise on them.
>
> > and FE5650 Rb
>
> The FE Rb’s tend to have a lot of spurs on the output. In some cases that
> can get you in trouble.
>
> > as the ref. I've tried Rb+MV89A
>
> If the MV89A is working properly, it should be a pretty good source. Based
> on some of the prices I’ve seen on the internal China market, you might get
> a couple of them as sources.
>
> > and Rb + SMY01 signal generator, same
> > performance. The 2nd-hand 53132A,PM6690,SR620 about 600~800$ here in
> China.
> > I'm trying not to get one unless necessary. If I have get one to compare
> > the performance, what's your suggested model?
>
> The SR620 is a good counter, so is the 53132. They both can have problems.
> The 53132 display wears out and it’s power supply can fail. The 620 can run
> a bit hot, which kills a variety of parts in it. It’s better to pay a bit
> more for one you can actually check out before you buy than to get one
> shipped in.
>
> >
> >
> >> 4) Have you tried jumping the 10 ohm resistor on the regulator output?
> (it
> >> may not be helping things …)
> >
> > I'll try to remove that tomorrow
>
> It may be allowing the supply to drop a bit when the chip goes into some
> sort of computation. Often these things happen at just the wrong time …
>
>
> ————————
>
> If you have a CPLD and a MV89:
>
> 1) With a 10 MHz sine wave  out of the OCXO, you need to convert it to
> logic first. A biased input is a pretty good way to do this.
>
> 2) Generate 200 or 400 ns wide pulses out of the CPLD for testing. That
> will eliminate any issues from the 5 MHz crystal in the MV-89.
>
> 3) Keep the PCB as simple as you can. You need at least a double sided
> board (one side ground plane). If you can get a cheap 4 layer board, go for
> it. A full internal ground plane is a good thing.
>
> 4) Route the high speed signals (like the OCXO output) through solid
> connections. Flying wire leads are not a good idea. Mounting a MV89 direct
> to the PCB is a good way to do things. SMA connectors are also good.
>
> 5) If you have an oscilloscope or can borrow one, take a look at the
> signals on your board. Even a quick check can tell you a lot about signals
> that are not what they should be.
>
> 6) Be careful of ground loops and power supply issues. I’ve spent a *lot*
> of time on breadboards that didn’t work because I had power line noise
> running around.
>
> Good luck !!
>
> Bob
>
>
> >
> >
> > All of which is *plenty* good enough to make a decent counter.  That
> >> assumes that they are talking about accuracy (even 1 sigma) rather than
> >> just the resolution of the LSB. Specs are often confusing on parts like
> >> this.
> >
> > I guess the accuracy is not important in the interpolator scenario.  It
> has
> > a feature to output the result of delta_time / ref_cycle_time(it will
> > measure the 2cycle_time - 1cycle_time after the delta_time measurement
> and
> > do the float calculation).  All I need is this part(it's the fraction
> part
> > of refcnt). So if I can reach 90ps resolution they claim, the counter can
> > tell 1/1000 of one reference cycle. That's 3 digits.
> >
> >
> >
> > Thanks.
> > _______________________________________________
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