[time-nuts] tutorial on phase noise and PLLs?
kb8tq at n1k.org
Thu Dec 4 19:04:57 EST 2014
If you are using a simulator, you can *really* get confusing and toss in detector or divider noise floors ….
> On Dec 4, 2014, at 6:45 PM, John Miles <john at miles.io> wrote:
>> See how Fig 8 and Fig 9 provides two different cross-overs between the
>> noise responces, and how the higher bandwidth doesn't have a "hump" just
>> because the steered oscillators noise response get's sufficiently
>> high-passed by the loop PLL as for the lower PLL it humps up because of
>> them having comparable power (amplitudes yes, but their power adds, as
>> it is noice).
>> Maybe it is good enough for your purposes, but yes, I agree there should
>> be a better presentation about the problem.
> Another suggestion: fire up ADISimPLL and create a few different designs with various damping factors and combinations of VCO noise and loop BW. It'll only take a few minutes, and the resulting plots will show both the individual and summed contributions of the different noise sources in a way that will instantly clue people in.
> -- john, KE5FX
> Miles Design LLC
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