[time-nuts] The Trapezoidal Clocking

Bob Camp kb8tq at n1k.org
Sun Dec 14 21:45:04 EST 2014


…. but …

Low edge speeds => poor signal to noise => high jitter.

The result is a clock that aligns, but has high(er) jitter compared to a conventional square wave clock. Most of the “lower phase noise / lower jitter” progress in CMOS logic has gone hand in hand with faster edge rates. 


> On Dec 14, 2014, at 8:27 PM, Magnus Danielson <magnus at rubidium.dyndns.org> wrote:
> Bob,
> On 12/14/2014 02:10 AM, Robert Darby wrote:
>> This is an paper that may be of some interest to those interested in
>> clock distribution.  The author, Jinyuan Wu has done considerable work
>> on FPGA TIC's with Fermi Lab.
>> http://www-ppd.fnal.gov/EEDOffice-w/Projects/ckm/comadc/TrapezCLK1b.pdf
> How incredibly cunning!
> Cheers,
> Magnus
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