[time-nuts] schematics of frequency counter

Charles Steinmetz csteinmetz at yandex.com
Thu Dec 25 15:31:01 EST 2014

In reply to Li Ang, Bruce wrote:

>The CLK1 input circuit produces an output incompatible with the 3.3V 
>CMOS device it drives.A pair of pnp transistors in an otherwise 
>similar circuit is capable of producing a 3.3V CMOS compatible output signal.
>Using independent voltage dividers to bias the transistor bases is a 
>bad idea in that resistor tolerances may lead to a dc input offset 
>of several tens of millivolts even with 1% resistors,

I agree with Bruce.  The circuit below avoids these problems.  It is 
generally known as a "Wenzel squarer" (after Charles Wenzel, who 
popularized it -- see 
I revised and simulated a circuit I use all the time for 5v output to 
produce a 3v output, but I did not build it, so some adjustment may 
be required.  All resistors should be metal film.  The 1uF capacitors 
should be X7R, and the 100nF and 10nF capacitors should be 
NP0/C0G.  "Design center" for this circuit is a 10MHz input at 1Vrms 
(not shown is the 50 ohm input resistor that would terminate a 1Vrms, 
50 ohm source).

Note that the circuit needs some "overhead" voltage to bias the PNP 
devices, so a 5v power supply is shown.  Both this supply and the 
base reference supply need to be quieter than the precision you 
expect from the circuit.  The decoupling shown should be 
significantly better than required for your purposes here, but keep 
this in mind if you push on to significantly higher resolution.

I don't know what the highest frequency you expect to count is.  The 
3906s are as fast as the 3904s you are using, and are fine at 10MHz 
and even up toward 100MHz -- but at some point you would need faster 
transistors.  The MMBT5179 and BFT93 are two possibilities.  Note 
that these faster transistors also reduce the sloping of the top of 
the "square" wave output (which is due to capacitive feedthrough of 
the B-E junction of the input transistor).  With less current 
available from this feedthrough (due to lower junction capacitance), 
you will probably need to increase the output resistor (R6) to 
achieve a full 3v output level if you use faster transistors.  [Note 
-- the attached simulated scope traces show the output (Q2 collector) 
and reference (Q2 base).  You want to keep Q2 out of saturation, so 
the peak collector voltage needs to be no more positive than the base 
voltage, as shown.]

Note also that the input capacitor and the emitter coupling capacitor 
limit the lowest frequency you can count.

Finally, note that the circuit does not have a lot of gain, so the 
low-signal limit is higher than on most commercial counters.  A 
0.2Vp-p input produces a 0-2.6v, mostly sinusoidal output.  By 1Vp-p 
input, it is nicely square.  I'd limit the input voltage to 
~5Vp-p.  If you need better sensitivity, you can add a preamp.   (If 
this were to be used as a general-purpose counter, I'd design a 
limiting preamp for the input.)

Best regards,


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