[time-nuts] schematics of frequency counter
kb8tq at n1k.org
Fri Dec 26 12:15:17 EST 2014
> On Dec 26, 2014, at 9:21 AM, Magnus Danielson <magnus at rubidium.dyndns.org> wrote:
> On 12/26/2014 02:38 PM, Li Ang wrote:
>> Hi Charles & Bruce
>> I'm not good at analog circuits. My circuit is modified from wenzel's,
>> since RF pnp transistor is harder to get. I would like the front end works
>> at 300MHz.
>> My questions:
>> 1) why the difference of DC bias of the 2 NPN matters? I thought only the
>> frequency part is useful to a counter, amplitude information is useless
> For time-interval measurements, offset errors can translate to time errors. HP filed a patent for a calibration devise and compensation routines that aimed to separate offset errors from time offsets, such that proper compensation can be done. This was done for the HP5370A in mind. The calibrator consists of RF phase-splitters and RF-relays such that one can attempt different polarities on the inputs.
> Naturally, these offset can depend on temperature, and you want to make sure that temperature stability of your input and input offset is low enough not to completely spoil your measurements.
> So, I agree that you would like to make sure that both sides of the differential pair should have a common voltage bias source, to make sure that the nominal current splitting between the transistors is about the same and thus the nominal offsets of the I/V for the NP-junctions balance each other out... and those is temperature sensitive. Similarly, usually you want both inputs to see about the same source resistance, in order to reduce offsets.
… but …
If the objective *is* a frequency only counter:
It’s an “AC” ( = frequency) system. The “DC” ( = time) offsets pretty much do not matter. The same is true of the temperature sensitivities. They contribute to a static (or slowly varying) time offsets. The static part of the time offset drops out of a frequency calculation. The slowly varying time offsets are not a big deal for normal gate time frequency measurements. Yes, if you are running 10,000 second gate time frequency measurements it would matter. That’s not a common thing to do. Very few frequency counters support > = 1,000 second gates. For most people 10 seconds is a bit slow. 100 seconds gets really boring really fast.
In a frequency only input channel the stages are AC coupled rather than DC coupled to get around the accumulation of small offsets. That is a reasonable solution to using NPN transistors in the input channel. With AC coupling you *will* have a lowest usable frequency. If that frequency is > 10 KHz you can have a fairly simple design. If you want to go down to 10 Hz the design gets more complex.
Commercial counters are targeted to hit the widest audience possible. They get a lot of features on them. It is a rare customer that uses all of those features. In the case of a home built design, it is *much* easier to target a sub-set of those features.
>> 2) what's is the C4 in your circuit for?
>> 3) If the noise is more important than the gain, what kind of transistor
>> should I choose? The Ft near 300MHz ones(BFS17, 2SC9018) or Ft far beyond
>> 300MHz ones(BFP420, BFP183,BFR93) ?
> You attempt to gain yourself out of having noise be the dominant source. A too high bandwidth will open up unnecessary noise, as it increases with bandwidth, at the same time you want high enough bandwidth for the output to support the slew-rate you want. For clock signals, a single amplifier stage usually suffice, but for lower frequency signals as coming from the beat frequency in a DMTD setup you want several stages of increased bandwidth and slew-rate.
A DMTD is a good example of just how custom an input channel *can* get. They are optimized to the point that they work over a range of less than a decade and often less than an octave. They also have fairly tight input level requirements. They do a fine job, but are very specific to a single input. In a general purpose counter this is not anything you would wish to do. There are a lot of things you *could* do that you probably *should* not do.
Of course for *testing* the counter a very simple input circuit that worked at only 10 MHz would be fine. A logic gate, two capacitors, two resistors, and a coil would do it. There is an exception to every rule.
One *should* understand what’s going on in the various parts of the counter. Feature tradeoffs should be made after understanding what is involved in the tradeoff. Research is a good thing. In some cases side project style experimentation may be required to fully understand a subject. All of that should not get in the way of making progress on a working example of the counter. Getting hung up for months on one element of the design cycle is not the best way.
> The difficulty of the gain approach is that no amplifier will be optimum for a large range of frequencies. Look at the CNT-90/PM6690 for instance, it even had a dual bandwidth buffer-amplifier in parallel in order to achieve good performance even below 10 kHz.
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