[time-nuts] schematics of frequency counter

Bob Camp kb8tq at n1k.org
Sat Dec 27 09:58:39 EST 2014


(In reply to several posts. It’s easier for me this way)

Ok, that’s good news !!! (and useful data)

Your counter performance degraded a bit when you put in 5 db and not much when you put in 8 db. 

It’s also maybe *too* good news. I suspect that cross talk between the channels may be impacting your results. 

Next step is to try it with two independent sources and a bit more attenuation. When you try it with two sources, you need to attenuate first one source and then switch the attenuators to the other source. That will help you see if crosstalk from one channel is more of a problem than from the other channel. 

One parts hint: 

Cable TV attenuators are much cheaper than their fancy 50 ohm MIniCircuits cousins. They are also something you can pick up down at the corner electronics store. For this sort of testing they are perfectly fine to use. At this point in the testing the mismatch between 75 ohms and 50 ohms is not a big deal. You will need to adapt connectors, but you probably still will save money. 


Op-amps that have enough bandwidth and performance for a high input impedance counter input are rare items. They also are not cheap. Often they come as some sort of current feedback part with low(er) input impedance. If you want your counter to work to 300 MHz, it should accept a 300 MHz square wave. That might mean passing the third or even the fifth harmonic of the square wave. An input channel with 900 or 1500 MHz bandwidth is quite a challenge. 

One very simple solution is to just grab a high speed comparator like the one used by Fluke / Pendulum (ADCMP565). Drive it directly with your input or clock. Make it your front end device. That’s not an ideal solution, but it will give you the bandwidth and a reasonable input impedance. It requires messy things like a negative supply  or a “fake” ground (so would the op amp). It also has an ECL output that needs to be converted to match your FPGA ( hint: use the clock inputs, they are LVPECL compatible). Driving into the FPGA with a differential signal is probably needed to reduce crosstalk.

No matter how you do it, input channels are *not* an easy thing to do properly. Even on commercial counters, they often are easy to fool. Designing one is only the start. Fully testing it is equally complex. 


Do not underrate your skills in any way. You are doing far more on this project than any of the rest of the list members have done. We have talked and talked forever about these chips. We talk a lot about these ideas. We suggest lots of complex solutions to various possible problems (like the expensive comparator I suggested above). What we almost never do is actually build a counter. If we build something we don’t fully test it. I have never seen any list member share their results the way you have. I suspect that most of us (yes this includes me) are a bit to scared of the response. 

Please do not stop your work. Keep letting us know how it is going. This is very exciting !!!


> On Dec 27, 2014, at 8:22 AM, Li Ang <lllaaa at gmail.com> wrote:
> Hi Bob,
>  Here is the data and test scheme.
>  It does not show much difference.
> 2014-12-26 22:12 GMT+08:00 Bob Camp <kb8tq at n1k.org>:

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