[time-nuts] Beginner question - unexpected possible jitter in 1 PPS output of Motorola ONCORE UT+ module

David Feldman wb0gaz at yahoo.com
Sun Jun 1 18:54:32 EDT 2014

Thanks to Tom, Jean-Louis and Chris for all of the helpful advice.

Problem is now fixed.

First problem was obvious - the 74HC390 I use as a divider clocks on negative-going transition. Added inverter, and the problem appeared to still be present (!)

Next problem was not so obvious - my very cheap benchtop chinese frequency counter (a Zhaoxin HC-2700L, bought on ebay, and retrofitted with a divided-by-two Pletronics 26 MHz VCOCXO as timebase, which were for sale cheaply on ebay a few years ago) turns out to have a bug/defect in the "totalizer" mode; when count transitions from 99 999 999 to 00 000 000, the counter ignores its input for a few milliseconds while it processes something, so my original plan to count for 10 seconds (expecting to see 30 000 000, which is 130 million with the hundred-million digit wrapped off) didn't pan out. Small change to the counter circuit and I now count a series of 1-second intervals, each of 13 MHz reference oscillator in the counter.

I adjusted the counter's timebase VCOCXO bias input so that counting for seven 1-second intervals shows 91 000 000 (13 000 000 * 7). There seems to be a +/- 1 count uncertainty, likely due to absence of synchronization between the counter's timebase and the 1 PPS signal, but this accomplishes what I set out to do, which was a cheap-and-dirty (but certainly not quick!) calibration of the counter's timebase.

Thanks for everyone's advice and support!


>To: jl.oneto at free.fr, Discussion of precise time and frequency
>	measurement	<time-nuts at febo.com>
>Subject: Re: [time-nuts] Beginner question - unexpected possible
>	jitter in 1 PPS output of Motorola ONCORE UT+ module
>	<CABbxVHvpyUYZfP7=zztTKRXGr+F=k7DBYCzNLwAG04Tr=3_qMw at mail.gmail.com>
>Content-Type: text/plain; charset=UTF-8
>I posted here some days ago an admission that I did exactly this by
>accident once.  It is a very hard problem to debug because everything works
>just fine, except for the very high jitter.   So I go looking for noise and
>what not.    The problem was a wrong number of inverters.
>On Sat, May 31, 2014 at 7:58 PM, Jean-Louis Oneto <jl.oneto at free.fr> wrote:
>> ..... So if your divider is clocked on the falling edge of the 1PPS, you
>> can expect a 1 ms jitter...
>Chris Albertson
>Redondo Beach, California

More information about the time-nuts mailing list