[time-nuts] Modeling vs reality question re my TIC

[Bob Stewart]

Hi Chris,

I don't think it's a software issue, as the voltage doubled when I halved the VRef - which is what would be expected.  Also, the voltages tracked the 5334B when I still had it connected, except that the TIC seems more precise and less noisy.  Then again, the 5334B was being fed with 8 ft of RG-58U.  What I'm seeing with the TIC is exactly what I would expect to see, only better, if that makes any sense.  Maybe the LTSpiceIV models are where the problem lies.


Let me clarify the caps.  This is an 18F2220 PIC.  The pin cap is 5pf.  There is an internal CHOLD in the ADC which is listed as 120pf.  Here is a screenshot of the relevant page.


http://www.evoria.net/AE6RV/TIC/ADC.png

Bob




>________________________________
> From: Chris Albertson <albertson.chris at gmail.com>
>To: Bob Stewart <bob at evoria.net>; Discussion of precise time and frequency measurement <time-nuts at febo.com> 
>Sent: Monday, March 10, 2014 3:26 PM
>Subject: Re: [time-nuts] Modeling vs reality question re my TIC
> 
>
>On Mon, Mar 10, 2014 at 12:12 PM, Bob Stewart <bob at evoria.net> wrote:
>
>> A range of 0.715V-2.38V is totally outside my expectations.  The only way I can get close to these values is if the internal CHOLD in the PIC is only a fraction of the 120pf they say it has - say 20pf.  Any thoughts would be appreciated.
>
>Could it be a software issue?  20pf seems about right for a normal
>input pin in a typical chip.  They all have diodes protecting from
>static and 20 pf seems like what I'd expect.     You say there is an
>internal 120 pf cap inside the PIC?  If so you'd need to connect that.
>It may be that you are not doing that correctly or at the time you
>think you are.   I'm guessing and we'd need both the spec sheet and
>your code to know for sure.
>-- 
>
>Chris Albertson
>Redondo Beach, California
>
>
>