[time-nuts] Divide by five

Bob Camp kb8tq at n1k.org
Sun Nov 9 15:47:05 EST 2014


> On Nov 9, 2014, at 3:31 PM, Chris Albertson <albertson.chris at gmail.com> wrote:
> On Sun, Nov 9, 2014 at 10:11 AM, Bob Camp <kb8tq at n1k.org> wrote:
>> That may (or may not) give you the best ADEV on the output. My guess is
>> that the filtering algorithm will need to be a bit more complex. NTP’s aim
>> is mainly to throw out bad clocks and pick one as best. We would more
>> likely want to combine the outputs and use all of the good clocks we have.
>> The idea is to improve on the ADEV of the *best* source you have available.
> No, not "pick one as best".  NTP does not pick the best clock.   NTP finds
> the subset of clocks that track each other.  Clocks are allowed to enter
> and leave this set.  NTP then computes a weighted average of the clocks in
> the set.   Pretty much what you said you wanted.
> These two algorithms are used.  Conceptually that are run one after the
> other but actually they run together in a loop forever
> 1) clock selection <http://www.eecis.udel.edu/~mills/ntp/html/select.html>
> 2) clock cluster <http://www.eecis.udel.edu/~mills/ntp/html/cluster.html>

The clock that’s in the middle of the cluster is the one that is “best” and gets flagged as such.


> You would not want to use this exact algorithm but something like it.  I
> think the basic idea is simple:  Reference clocks should tend to cluster
> around correct behavior.  In other words our set of reference clocks is not
> biased.  I don't think there is any way to detect bias unless you add more
> reference clocks.
> I would very much avoid an FPGA based CPU. You likely will need to add both
>> flash and ram to the FPGA. Once you are done, you have a $30 gizmo that
>> replaces a $1 chip. You also have a tool chain for your code that is far
>> from “low barrier to entry”. It’s a great solution for something like video
>> processing that needs TONS of bandwidth. We are very much on the other end
>> of that stick.
> I agree.  Unless the whole this is FPGA based and you have enough free
> gates.  Otherwise it is not good to use something so complex to simulate a
> $2 part.
>> --
> Chris Albertson
> Redondo Beach, California
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