[time-nuts] Homebrew frequency counter, need help
time-nuts at kasperkp.dk
Fri Nov 28 16:57:16 EST 2014
On 11/27/2014 03:08 PM, lllaaa wrote:
> Hi guys,
> I've just get my homebrew counter working. And the resolution seems 10x
> better than my RACAL DANA 1992.
> This counter is heavily inspired by the idea from Kasper Pedersen.
> STM32F051RB & EMP240T100C5 do the control and counting job. TDC-GP22 as
> the interpolator. Linear regression is done by CPU.
> There are no fancy analog front for both signal path and refclk path.
> I'm using two SN75ALS176 and the schmitt input of CPLD to do the job.
> I've noticed that the 10s gate does not get more meaningful
> digits(looks worse than 1s gate). So here are the questions:
> 1) I'm wondering if I could say this is an 11 digits/s counter?
> 2) How can I improve that? Is it limited by the 485 transceiver? I can
> switch to a faster MCU, that gets more measures per second, but I think
> that only gets no more than 2 stable bits.
A few things to try, and learned:
Try measuring the reference against itself, triggering on the same edge
you clock the cpld on. If your VCC is wandering, your threshold will
wander, and you get wandering phase out of the schmitt trigger in the CPLD.
When I built my counter, I had much fun with my 'front end' (AC04s)
having variable heating, and thus variable delay, depending on slew rate.
I ended up giving each input channel its own low noise regulator to keep
crosstalk from going through VCC. I think I calculated that, for a 10MHz
10dBm signal, 6mV threshold error is 100ps.
I assume you can pick which edge to trigger on. Measure the reference
against itself, and read out interpolator (phase) data on either edge.
When I did my counter, I had ground current flowing through the coax
between the counter reference input, and the house standard. I had been
silly and chosen a low cutoff frequency for the dc-block capacitor in
the reference input, which meant that the resulting voltage over the
coax shield resistance got through the dc-block, and caused phase
modulation. On the rising edge, the noise was low. On the falling edge,
it was nasty and wandering, since when you add LF to 10MHz, and then
slice it, the pulsewidth varies.
>From bad experience, try dumping out adjusted timestamps of
almost-10MHz, and plot actual timestamp vs predicted timestamp. It will
show you if you have 10MHz crosstalk, or, if as I did, you added the
interpolator value instead of subtracting it. In my case the counter
appeared to work most of the time, while giving wrong readings all of
And congratulations on getting it working.
(When getting 10MHz out of FEI5680As, mine had ferrite blocks around the
dsub connectors, and while I could get a cleaner signal by shorting GND
to shield on the connector, it was better again when I bypassed the
connector entirely and ran coax.)
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