[time-nuts] LTE-Lite module

Jim Lux jimlux at earthlink.net
Sun Oct 19 17:00:56 EDT 2014

On 10/19/14, 1:08 PM, Bob Camp wrote:
> Hi
>> On Oct 19, 2014, at 3:35 PM, Charles Steinmetz
>> <csteinmetz at yandex.com> wrote:
>> Bob wrote (alluding also to something Poul-Henning wrote):
>>> The phase comparison part of the PLL is pretty straightforward if
>>> you are looking at two RF frequencies. An XOR gate is one
>>> solution, there are many others. Getting something like 100 to
>>> 200 ns full scale on the phase comparator makes the rest of the
>>> gizmo much easier.
>> All true.  However...
>>> A 12 bit ADC on a MCU will get you to 100's of ps per bit.  That
>>> is more resolution (it's < 1 ns) than you need for this.
>> Getting an ADC to sample fast and accurately enough to provide that
>> honest resolution is not trivial.  And if you have that, you'll
>> almost certainly have the resources to do the phase comparator
>> digitally, too, which brings many advantages -- so I see no reason
>> to use an analog PC.
> If you take a look at some of the newer ARM MCU’s they are getting
> 13+ solid bits out of their ADC’s at a > 10 KHz rate. That’s more
> than good enough for anything you are trying to do with this design.
> There’s no need to make it any more complex.

I'm using the Freescale Kinetix K20 parts, which have 16 bit 
differential input ADCs, and built in averaging.  The raw ADC can sample 
at about 400kHz.

You can easily get 14 bit performance from these at tens of kHz rates.
I need I/Q, so I sample two inputs at 50 kHz (read one, then the other) 
without averaging (so they're about 2.5 microseconds apart), and then 
decimate them through a 2 stage CIC and a 13 tap FIR filter down to 200 
Hz.  This takes about 60% of the processor running at 48MHz.

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