[time-nuts] Ultra High Stability Time Base Options for 53132A

Charles Steinmetz csteinmetz at yandex.com
Tue Apr 14 03:11:30 EDT 2015

John wrote:

>All other things being equal, it's desirable to minimize the time 
>spent in that region of the waveform.  It doesn't necessarily hurt 
>to choose a faster logic family, as long as the process noise and 
>device gain are otherwise compatible with the decision.  Random 
>jitter on the 7.5 GHz ADCLK905 is specified at around 60 
>femtoseconds, after all.  A residual PN test at 10 MHz on an 
>ADCLK905 ends up at around -135 dBc/Hz at 1 Hz just like many other 
>slower comparators, a figure that's good for 1s ADEVs in the E-14s

>To square up a 10 MHz signal from an OCXO it's hard to beat a simple 
>diff amp with a pair of bipolars, a la Wenzel.

I have found the same when squaring 5-10 MHz sine waves.  I have used 
the optimized Wenzel circuit shown below many times, always with 
excellent results.  More recently, I have tested the LT1719 squarer 
also shown below.  Both exhibit residual PN of less than -130 dBc/Hz at 1 Hz.

Best regards,


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