[time-nuts] FLL errors

Azelio Boriani azelio.boriani at gmail.com
Fri Aug 28 06:16:29 EDT 2015

OK: the XOR gate with an RC is a defective PLL and a defective FLL. It
is a simple way to have an idea of what an xLL should be but of no
serious use.

On Fri, Aug 28, 2015 at 5:03 AM, Charles Steinmetz
<csteinmetz at yandex.com> wrote:
> Azelio wrote:
>> Since I have not found a strong definition for the FLL, I assumed: if
>> PLL= zero phase error (and so zero frequency error) the FLL= same
>> frequency, random phase. The XOR with RC is a perfect fit for this:
>> same frequency all the time but phase determined by the EFC needed to
>> have that frequency. The phase = constant, in the XOR/RC is true as
>> long as the VCO is stable and the EFC has not to be altered to steer
>> the VCO, that constant is not a design parameter but walks with the
>> VCO frequency movement.
> The "x" in "xLL" refers to the parameter that is measured, which the "LL"
> attempts -- more or less successfully, depending on the particular
> implementation -- to drive to zero.  (More correctly, the "LL" attempts to
> drive the measured quantity to a constant.  Many PLLs do not lock with the
> controlled oscillator at 0 phase relative to the reference oscillator, they
> lock near 90 or 180 degrees.  This includes PLLs with XOR phase detectors,
> which lock with the VCO at ~90 degrees to the reference oscillator.)
> An XOR measures the *phase* difference between two oscillators, and an xLL
> with an XOR detector is, therefore, a PLL.  If it is incapable of locking
> stably, that does not make it an FLL -- it is just a defective PLL.
> An FLL measures the *frequency* difference between two oscillators and
> attempts to drive it to zero.  (As I mentioned in my previous post, because
> of systematic biases, the FLL actually drives the frequency difference to a
> low value near zero.  Carefully engineered dither can be added to
> redistribute the error stochastically around zero.)
> Best regards,
> Charles
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