[time-nuts] schematics of frequency counter

Bob Camp kb8tq at n1k.org
Mon Jan 5 19:59:51 EST 2015


> On Jan 5, 2015, at 6:26 PM, Li Ang <lllaaa at gmail.com> wrote:
> Hi
>   I've confirmed that it's 198ns between start and stop with my racal dana
> 1992. I've spent days to learn how to compensate this 2ns in Quartus.
> However, it's not something easy for me to do.

It’s not something that anybody I know finds easy to do. The constraints in the sdc file are not as easy to work with as they could be. The Altera people are using a language that was defined by others. I find that many of the definitions are backwards from the way one would expect them to be.  Their older timing approach was easier to understand, but it was not “industry standard”. 

> I will ask some
> hardware colleague for help.

Expect to buy them lunch. Hardware people are always hungry when asked for favors :) I’d bet the timing stuff is not something they enjoy doing either. 

>   Two days ago, I assembled my 2 mv89a to PCB ,put them into 2 metal
> boxes.

Each box with it’s own power supply or both on one supply? Because of the high current draw of the OCXO, two supplies (even wall wart ones) are better than a single common supply. 

> The test time is longer than before since it's in the holiday. These
> data confused me more. I got bigger frequency difference if sig=ref.

That is a bit weird. 

>   Things are getting more and more compilcated. :(

I would check the splitter and cables first. It may be something fairly simple (like a loose ground).


> raw data: http://www.qsl.net/bi7lnq/freqcntv4/test/20150105/0105.zip
> Thanks
> 2014-12-29 4:35 GMT+08:00 Bob Camp <kb8tq at n1k.org>:
>> Hi
>>> On Dec 28, 2014, at 9:19 AM, Li Ang <lllaaa at gmail.com> wrote:
>>> Hi Bob,
>>>  I did some test according to your suggestions. DUT is a symmetricom x72
>>> rb oscillator. Also, I've tried signal generator as the DUT. R&S SMY01 is
>>> not as good as HP8662A but that the best I've got. The signal geneator is
>>> also using FE5650 as ref clock.
>>>  According to my test with the TDC today, this unit is not producing
>> very
>>> stable data.
>>>  I don't have accurate pulse generator, so this is how I test the TDC:
>>> 0) power the board with battery.
>>> 1) use FPGA to generate time pulse:

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