[time-nuts] 5>10 doubler

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Jan 27 17:57:24 EST 2015

Using the square law characteristic will inevitably increase the phase noise floor particularly in the flicker region with respect to just using the switching characteristic of a JFET, diode or BJT  (non saturated).The only viable solution is to use better filtering of the output of a switching multiplier.If you intend to use a diode ring based mixer configuration diode connected (collector shorted to base) npns such as 2N222's are significantly quieter (as shown by NIST) than schottky diodes for frequencies below 40MHz or so.

     On Wednesday, 28 January 2015 8:25 AM, Charles Steinmetz <csteinmetz at yandex.com> wrote:

 Andrea wrote:

>Now I have some 5MHz DOCXO. I have started to experiment with them
>and I would like to build a frequency doubler.
>      *  *  *
>By the way, I see that really many of the 10MHz reference out there, are in
>effect doubled 5MHz ones so build a doubler seems reasonable for me.

One thing to watch for is the 5MHz leakage component.  If you are 
going to use the 10MHz standard for time-nuts experiments, the 5MHz 
component needs to be WAY down (< -80dBc) or you will get funny 
periodic ripples in stability plots.  Despite having two 5MHz traps, 
one recently published design suppresses the 5MHz component only 
about 52dB below the 10MHz output, and the 20MHz and 30MHz components 
are also only -50 to -55dB.

For this reason (and some others, see discussions over the last 
several months in the archives) I prefer a doubler built with a 
quadrature hybrid coupler and a balanced mixer.  There is a write-up here:


I recently revived an old, stalled project to develop a JFET 
push-push doubler for use at 5MHz (see schematic below).

FETs with very high transconductance and very small pinchoff voltage 
(what a tube designer would call a "sharp cutoff" characteristic) 
(e.g., 2SK369, BF862, etc.) are attractive on first look because they 
can operate with lower conversion loss or even some conversion 
gain.  However, they are not well suited for doubler duty for two 
reasons: (i) their characteristics have a very short range of 
2nd-order curvature, so in order to keep noise down they must be 
driven into regions of higher-order distortion and therefore generate 
lots of spurious energy; and (ii) they are devilishly hard to match 
well enough to suppress the input frequency feedthrough.  Note that 
you also need to put enough voltage on the FET drains to get them 
well into the saturation region -- a Vcc of 5v is not enough.  Again, 
the penalty is lots of spurious energy.  So, the lower conversion 
loss of sharp-cutoff FETs is not the benefit it might at first appear 
to be -- it is much easier to add gain after the doubler than to 
remove unwanted spurious mixing products.

The design below uses medium-cutoff FETs and a Vcc of 15v (I found 
that J111 and J310 work best and can be matched sufficiently with a 
one-point match; 2N4416 and others also work, but are fussier and 
would benefit from a 2- or 3-point match).  At an input of 500mVrms, 
their long 2nd-order characteristic is used efficiently to generate 
10MHz with relatively little spurious energy.

I had no problem finding one or more FET pairs matched to within 1mV, 
given 20 devices from the same lot (YMMV).  With properly adjusted 
traps at 5, 20, and 30MHz, all spurious responses were below 
-80dBc.  The inductors can be commercial RF parts with Q of 200 or so 
(I used some high-quality through-hole RF inductors I had on hand -- 
I doubt any SMD inductors will work).  The trap capacitors should be 
C0G/NP0 ceramics for the bulk of the capacitance, plus very small 
trimmers (I used 27pF, 27pF, and 100pF plus 0.2--6pF glass piston 
trimmers).  I wound the two transformers on Mix-61 toroid cores (each 
winding is 20 turns on a FT37-61 core -- the inductance is a little 
lower than called out).  Mini-Circuits parts (or equivalents) may also work.

Best regards,


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