[time-nuts] ***SPAM*** Re: 5>10 doubler

Charles Steinmetz csteinmetz at yandex.com
Sat Jan 31 13:37:47 EST 2015

Andrea wrote:

>the square-law characteristic of devices should be avoided, so the
>configuration of the doubler must be some sort of "ideal" full wave rectifier

I disagree strongly with this, at least where push-push JFET doublers 
are concerned.

If you look at the schematic Bruce posted on his site, which uses a 
pair of J310 FETs driven into the pinch-off region, it runs the FETs 
from 0 to about 21mA.  My circuit, when using J310s, runs the FETs 
from about 1mA to about 16mA.  In both cases, when the FETs are 
conducting they are operating as common-source linear amplifiers, NOT 
as switches.

In either case, when one FET is drawing low (or zero) current, the 
other one is drawing high current.  The theoretical noise improvement 
due to running the low-current FET past the pinch-off point is, in 
practice, totally swamped by the noise from the other FET.

In order to realize a useful reduction of noise, the FETs would have 
to switch hard, from "off" (beyond pinchoff) to "full on" (with 
Vgs=0) -- but JFETs don't work like that, unless you drive the gates 
hard with square waves (that is how commutating mixers such as the 
ones designed by Ed Oxner and the later "H-mode" mixers work).  See 
below for a schematic of an Oxner mixer using a quad JFET (but note 
that commutating mixers generally use MOSFETs).

When my circuit is normalized for 50 ohm output (by using a 4:1 
transformer at the output -- which is the preferred method of driving 
50 ohms with it) and the bias and drive are adjusted for the same 
currents as Bruce's circuit, the models predict almost identical 
noise from the two circuits.  As a real-world check, I adjusted the 
bias conditions and drive on my breadboard doubler to give FET 
currents from 1 to about 22mA, and the measured noise decreased by a 
fraction of a dB.  (The spurious distortion products rose somewhat, 
but not nearly as much as when one drives the FETs beyond pinch-off.)

So no, running the FETs in Class AB or B does NOT confer a material 
noise advantage compared to running them in "barely Class A," as my 
design does.  It does, however, create an exponential explosion of 
odd-order distortion products that must be removed if the circuit is 
to be useful for time nuts purposes.  So in my view, the "barely 
Class A" push-push JFET doubler is clearly superior to its Class AB 
or B cousin.

>it's better to use diode-connected transistors like the 2N2222
>      *   *   *
>matching is very important, so monolithic doubles or quadruples could be the
>right choice, provided their other characteristics are compatible and the
>substrate connection is not a problem

[NB: this applies to a mixer-based doubler, not a JFET push-push 
doubler.]  Again, this is a theoretical advantage that is easily 
overshadowed in practice by the errors introduced by building one's 
own diode DBM.  It is not impossible to build a home-brew DBM that 
performs as well as a good commercial DBM, but it is not easy, 
either.  Just a small imbalance due to unequal winding spacing on the 
cores, small differences in stray capacitance, or geometric 
differences due to the packaging of the transistors used can easily 
create increased distortion products that are much worse than the 2 
or 3dB reduction of noise you might realize.  I'm not saying don't do 
it, just that the chances of improving things without causing 
collateral damage that is worse than the cure may not be high.

Best regards,


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