[time-nuts] Square to sine wave symmetrical conversion (part 2)

jerry shirá´€r radio.n9xr at gmail.com
Sat Jul 25 01:28:46 EDT 2015


If you are tearing into the oscillator for correcting the 20% duty cycle,
you may as well bypass the digital inverter at the output driving the
output pin.  The signal going into the inverter will be a sinewave.  The
reason it is at 20% duty cycle is that the DC bias running into the
inverter stage is too low for the digital device.  If the reason for the
20% is farther backstream then the sinewave could be distorted.  The phase
noise could then be poor.  But back there somewhere is a sinewave.  By
bypassing the inverter you will improve phase noise.  Yuo will probably
need a sine buffer at 10MHz to drive 50 ohms.

Jerry

On Fri, Jul 24, 2015 at 8:35 PM, Charles Steinmetz <csteinmetz at yandex.com>
wrote:

> skipp  wrote:
>
>  [the 10MHz output is] not even close to being symmetrical.  The waveform
>> on-portion (duty cycle) appears (surprising to me) to be much less than
>> 20%
>>
>> Now I'm under the assumption that proper rounding or conversion of the non
>> symmetrical 10 MHz square to a sine wave will be a bit more involved.
>>
>
> That means there are significant even harmonics present, including the
> second harmonic, which is a lot closer to the fundamental and, therefore,
> harder to remove by filtering (a perfect square wave contains only the
> fundamental and its odd harmonics).
>
>  Before I launch toward part two of this latest saga, I'd really be
>> interested in reading
>> suggestions and comments regarding methods to improve/fix the 10 MHz
>> waveform
>> symmetry.
>>
>
> You could do a lot better than 20/80 by simply using the 10MHz pulses to
> trigger a 50nS one-shot (astable multivibrator).  However, that is a
> quick-and-dirty solution, not a precision solution -- the duty cycle would
> wander around with temperature, power supply voltage, noise, and other
> factors.
>
> Alternatively, you could use very aggressive filtering, but that could
> degrade the phase noise of the output sine wave due to the temperature
> coefficient of the filter cutoff frequency.
>
> One sure way to get a symmetrical output would be to use a Dflop frequency
> divider to generate a symmetrical 5MHz square wave, followed by a frequency
> doubler to get back to 10MHz.  There would be a phase noise penalty, but it
> could be less than the phase noise penalty of a sufficiently aggressive
> filter.
>
> Finally, you could use the 10MHz pulse train as the reference for a 1:1
> PLL.  I suspect this would be the best way to go about it.
>
> Best regards,
>
> Charles
>
>
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