[time-nuts] Effect of EFC noise on phase noise

Gerhard Hoffmann dk4xp at arcor.de
Tue Aug 2 06:40:45 EDT 2016

Am 02.08.2016 um 09:14 schrieb Bruce Griffiths:
> Gerhard, please send me the LTspice files,  so I can compare it with  some of my circuits.
> The Groner preamp uses feedback to adjust the dc input at the input (paralleled) FET gate(s) to adjust the dc output to zero.  It uses a small value input coupling capactor with a high value resistor to bias the JFET (parallled BF862's). I had simulated a similar preamp architecture some years before the Groner article.
> I suggested a similar preamp architecture on EEVBlog  but the responses indicated that most of the respondents appear incapable of rational analysis and just regurgitate the conventional approach.
Some remarks:

1. don't get confused from my comments / aide-memoires in the source.

2. The transient simulation will wake up perfectly biased at t=0. If you 
want to
see the bias integrator working you must use the .ic statement to set the
integrator capacitor voltage to a start value, typically 0V. We have 
that already in the transformer inrush current thread.

3. The IF3602 is now available from Mouser.
It does not look like the symbol picture there. The price is somewhat 
obscene. Paralleling a lot of them
has some aspects of hybris, but at least the simulator does not care. 
Also the input capacitance is huge.
2 dozens of BF862 may be much cheaper and have less capacitance.
The Interfet data sheet is a joke. I did ask for something better but 
got no answer.

4. I have fiddled with the BF862 model to make it fit to the XSpice 
included in my Altium Designer.
You may use the one from NXP directly.

5. The noise of a JFET depends mostly on its capacitance and gm. More Gm 
is better, it is best
at maximum current. That would be Idss. Idss varies all over the place 
with JFETs and and with the IF3602
in special. 1:20 has been observed. In an ideal world, gm varies with 
the square root of the current, and
the input referred noise voltage varies with the square root of gm, so 
the noise gets better with the 4th
root of the current. This is not a strong dependence and a diminuishing 
ROI. More transistors at the same
current are better than one, but the input cap is larger. One gets the 
full advantage of more transistors
only with n times the current.

6. Given the price of the transistors I won't skimp on a heat sink and 
let them sweat a little bit.

7. Using IF3602 instead of IF3601 does not mean that you get matched 
pairs in the sense most people
are used to. But probably you won't get opposite outliers. The pairs 
cost more than 2 singles, but
are probably more consistent. Because of the 4th root it does not pay to 
regulate the bias of the
transistors individually unless you have a truly pathological case. 
Singles are easier to cool.

The measured Id vs. Vgs of my first 4 samples is in fet_preamp_notes.pdf.
Somebody has played with my data and extrapolated Idss. I wonder how he 
got the table out of the pdf,
enriched it and put it back in again. Some people are real hackers. :-)

8. Don't use more than 3 or 4 Volts of Vdd. It only adds heat and impact 
ionization in the channel.
That results in some gate current that hurts you with a 100 Meg bias 
resistor, noise-wise.
Avoiding gate current is even more important since it rises steeply with 

A Cascode is probably a must, alone b/c of the Miller. The feedback to 
the sources reduces the
swing at the drain, but with the cascode it works better.

9. The amplifier is AC coupled, but you can easily go down to 100 mHz. 
That won't impair your
Leeson plots close to the carrier. Take the dc for quadrature control 
from a different cheap
fet op amp. Your mixers may thank you with a longer life.

10. The version with the 20 paralleled op amps is at
< http://www.hoffmann-hochfrequenz.de/downloads/lono.pdf  >
In the same directory there is a .zip file with Gerber files and updated 

11. some pictures more at

12. I've got first silicon, ehem, FR-4 of my OCXO carrier board and also 
20 MTI-260 5 MHz
oscillators, still packaged in 20 gps-less Lucent units. While using 
multiple op amps
works so nicely, 16 sloooowly phaselocked MTI-260 that are wilkinson-ed 
together should
result in a pretty phase noise plot. Especially now that BVAs are no 
longer easily available.
Also, 1 of 16 cannot enforce a sudden phase jump; it would be slowly 
corrected back
by its PLL.

If you need Lucent spare parts other than MTI-260s, ask me.

  regards, Gerhard  DK4XP

-------------- next part --------------
*   JBF862: 1, Drain,  2,Gate,  3,Source
*  Ld  1 4  L=	1.1nH
*  Ls  3 6  L=	1.25nH
*  Lg  2 5  L=	0.78nH
*  Rg  5 7  R=	0.535 Ohm
*  Cds  1 3  C=	0.0001pF
*  Cgs  2 3  C=	1.05pF
*  Cgd  1 2  C=	0.201pF
*  Co  4 6  C=	0.35092pF
*JBF862  model parameters:
.model JBF862 NJF(
+ Beta=47.800E-3 	
+ Rd=.8 			
+ Rs=7.5000 		
+ Lambda=37.300E-3 	
+ Vto=-.57093		
+ Is=424.60E-12 	
+ Cgd=7.4002E-12 	
+ Pb=.5 			
+ Fc=.5 			
+ Cgs=8.2890E-12 	
+ Kf=87.5E-18		
+ Af=1				
+ )

* Semikolon-Kommentare kennt xspice nicht, Leerzeilen auch nicht,
* nach der 1. Zeile ohne + ist das Modell zu Ende
*+ N=1 				die kennt xspice / Altium DXP allesamt nicht
*+ Nr=2 				
*+ Betatce=-.5 		
*+ Vtotc=-2.0000E-3	
*+ Xti=3 			
*+ Alpha=-1.0000E-3	
*+ Vk=59.97 			
*+ M=.6015 			
*+ Isr=2.995p 		
* transconductance param A/V/V
* betatce	beta extponential TC
* rd		drain ohmic resistance
* rs		source ohmic resistance
* lambda	channel length modulation  1/V
* vto		threshold voltage
* vtotc		threshold TC
* IS		gate junction saturation current
* ISR		gate junction recombinaion current
* N			gate junction emission coefficient
* NR		emission coefficient for ISR
* xti		saturation current TC
* alpha		ionization coefficient
* vk		ionization knee
* cgd		zero bias G-D junction capacitance
* M			kennt auch LT-Spice nicht
* pb		gate junction potential
* fc		forward depletion capacitance coeff
* Cgs		zero bias gate-source capacitance
* Kf		flicker noise coefficient
* af		flicker noise exponent
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