[time-nuts] Shera revisted

Attila Kinali attila at kinali.ch
Thu Aug 11 15:06:12 EDT 2016

Hoi Bert,

On Wed, 10 Aug 2016 09:33:30 -0400
Bert Kehren via time-nuts <time-nuts at febo.com> wrote:

> I get repeated requests for info on Shera mainly for Rb applications. Shera 
>  has a successful history controlling Rb's.  Two things are a problem. The  
> AD 1861 is not only unavailable but also never intended for precise DAC  
> applications. The LTC 1655 makes a perfect replacement ,16 bits is more than  
> enough and covers range and resolution. What is needed is someone proficient 
>  with PIC assembly programming. We have the recommended changes.
> Second logic IC's are also outdated and hard to get. The solution is simple 
>  an Altera 32 cell 10 nsec. gate array, readily still available for less 
> than $  2, we have done a design and will gladly share once the PIC has been 
> modified  and tetsted.

What is your goal here? Simply a rebuild of the Shera controller
using current components?

I'm asking, because if you go the way of using a CPLD anyways, you could
throw in another $2 for an opamp to build a time-to-amplitude converter
(à la PICTIC II) and boost the resolutiong from 40ns to <100ps.
As you would be measuring the PPS relative to the local clock, you
would need only one "leg" of the PICTIC II (ie just one TAC plus a single ADC).

I guess you were refering to the 5M40Z from Altera, which can be had
for $1 at mouser. If you go slightly up in price to $1.5, you can get
an ICE40LP384 from Lattice with 384 LUTs, wastly enhancing your capabilities.

Yes, that would require a bit more than just changing a couple of
asm instructions, but would be worthwhile nontheless.
Especially if you are going to extend the system with pressure and
temperature compenstation anyways.

And I am with Chris on the topic of rewriting it in C, even if it's more
effort. Depending on what you actually do, part of the code can be
reused from open source projects out there, thus minimizing the actual work.

			Attila Kinali

PS: If you are doing the CPLD/FPGA coding in VHDL and need help, let me know.

Malek's Law:
        Any simple idea will be worded in the most complicated way.

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