[time-nuts] MV89A / MTI-260 / HP10811 carrier board
dk4xp at arcor.de
Thu Feb 25 21:20:27 EST 2016
Am 25.02.2016 um 20:06 schrieb Anders Wallin:
> Hi, looks quite useful!
> What's the benefit of the Xilinx CPLD (2-3 dollars/euro) over a PICDIV (<1
> dollar/euro) ?
My work would cost more than 1-2 €
> Sync-input for the PPS-output would be useful. Also a PPS LED that blinks.
> If the PPS-divider is directly under the OCXO it will get more or less warm
> - could that be a problem?
It is only useful as long as the oscillator is disciplined by the 1pps.
If the osc and the 1pps drift against each other, that is really bad.
I have written a VHDL implementation of the AD9901 phase detector
that could fit into the CPLD ( 6 Macrocells IIRC). It is a 1:1 translation
of the circuit in the data sheet. Still untested, would work for 1pps.
Maybe in V2.0. Getting sth. that works is more important now.
That the divider gets warm is unimportant. The resynchronisation
flipflop, 1pps driver and the squarers are what counts.
I'd like to have the blinkenlights offboard. I read about a Tektronix
sampling scope that had sampling jitter to the tune of a blinking LED.
> What's the idea with the mixer/DIY-PLL? Did you look at PLL-chips instead?
It is much like the circuit used by Riley and I had good results with it
> Would it make sense to have the time-constant for the PLL-loop adjustable
> with jumpers or a pot? Lock-indicator LED?
Maybe a decoupled testpoint for the tuning voltage, so one can watch it on
a meter. Unless it's so bad that there are cycle slips it is hard to say
automatically if it is locked.
And I hate pots. I want thin film fixed resistors.
> Could the board be 100mm wide with all the connections on one 100mm side,
> to allow vertical rack-mounting ('plug-in' unit) in a 3U enclosure?
You will need some shielding, both electrically and against air movement.
regards, Gerhard DK4XP
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