[time-nuts] low noise multiplication to 100 MHz

Mon Jan 25 17:05:39 EST 2016

Aaah - but then you need a microprocessor (and its noise if you're not 
careful) to control it. IMHO - too complicated an approach. Hard to beat 
a "careful" straight multiplier approach for simple or a phased locked 
100 MHz VCXO for the best phase noise.

Bill - N6GHz

On 1/25/2016 9:20 AM, Graham / KE9H wrote:
> There are clock distribution parts designed to do this low noise frequency
> conversion and distribution.
>
> Consider TI  LMK04100
>
> Ignore PLL1
> Put your 10 MHz as the reference input to PLL2.
> Set Internal VCO to ~1200 MHz
> Set the internal dividers to get 100 MHz out, and 10 MHz back to the PLL2
> phase detector.
>
> Get reasonable noise and 100 MHz output with your choice of 2VPECL, LVDS,
> LVCMOS output levels.
>
> If you have a dirty input clock/reference, or multiple sources, you can use
> PLL1 and an external crystal in a VCO to clean it up before you multiply it
> to 1200 MHz.
>
> And you can get up to four other frequencies out of the part at the same
> time.
>
> 150 fs class jitter.
>
> $13 cost, quantity one.
>
> --- Graham
>
> ==
>
>
>
>
>
> On Mon, Jan 25, 2016 at 9:22 AM, Bert Kehren via time-nuts <
> time-nuts at febo.com> wrote:
>
>> If not good enough an XOR with filter and one of the Crystek VCXO's
>> previously mentioned may do it.
>> Bert Kehren
>>
>>
>> In a message dated 1/25/2016 10:01:33 A.M. Eastern Standard Time,
>> magnus at rubidium.dyndns.org writes:
>>
>> Also, it  will be systematic, with idle tones. Because of the delay
>> elements used,  they will not be long-term static but move around.
>>
>> I agree, this is  quite noisy. If the noise is tolerable, it is indeed a
>> small solution. 100  ps 1-sigma for 5 MHz in 100 MHz out isn't what I
>> would consider  low.
>>
>> https://www.idt.com/document/dst/570-datasheet
>>
>> Cheers,
>> Magnus
>>
>> On  01/24/2016 11:12 PM, Bruce Griffiths wrote:
>>> Unfortunately the ICS570  (like all zero delay buffers) has an output
>> jitter approaching about 1000  times the likely RF ADC internal sampling
>> jitter. The resultant SNR  degradation may be a little excessive for this
>> application..
>>>   Bruce
>>>
>>>
>>>       On Monday, 25 January 2016  11:00 AM, Bert Kehren via time-nuts
>> <time-nuts at febo.com>  wrote:
>>>
>>>    With all the discussions in a small  100 MHz source I asked my project
>>> partner Juerg in Switzerland to run  some data on the ICS 570 that we use
>> on the
>>> majority of our projects  with excellent results. Using the HP53132A we
>> see
>>
>>> + - 1   count at E10-11 ignore the large jumps those come from the Tbolt
>>>   frequency  change to correct the 1 pps. Depending on the application
>> this  is an
>>> excellent  device.
>>> Bert  Kehren
>>>
>>>
>>> In a message dated 1/23/2016 6:02:23 P.M.  Eastern Standard Time,
>>> dk4xp at arcor.de writes:
>>>
>>> Am   22.01.2016 um 22:40 schrieb jimlux:
>>>> the oscillator is a HCMOS  output,  so figure swinging about 3.5V
>>>> Output.. I'm feeding  differential clock  inputs on ADCs.  I'll bet a
>>>> +/-  300mV swing would  work.
>>>>
>>>>> 4)Title said "Low  Noise"  needs better  definition as to what kind of
>>>>>   noise and how far down. Are we to  be  concerned about harmonic and
>> spur
>>>>> content as compared to  real random white  noise?
>>>> This is time-nuts.. it has to be   perfect..
>>>>
>>>> But realistically, my source is probably  going to be  about -90dBc/Hz
>>>> at 1 Hz, -125 at 10Hz, -145 at  100 Hz.  I'm  going up by a factor of
>>>> 10, so I'd expect  20 dB worse plus a  little..(nothing is perfect,
>> eh?)
>>>> Call it maybe -100 to -95 at  10 Hz, -125 to  -120 at 100 Hz and so
>> forth.
>>>> harmonics are   interesting: it's the sample clock into an ADC. So
>>>> harmonics of  the  100 aren't a big deal.  harmonics of the 10 or 20
>>>>   are.  If  you have significant 90 or 110 contaminating the 100,  then
>>>> you get  weird spurs..  (I had this problem on a  software radio where
>>>> the  50 MHz sample clock was  contaminated with some 66 MHz from the
>> CPU)
>>>>   Spurs cause the same issues.
>>>>
>>>> ON the other   hand... spurs that are pretty low don't make much
>>>> difference  if  you're digitizing a signal that is close to the noise
>>>>   floor: the spur  multiplied by the desired signal is usually lower  and
>>>> down in the  noise.  Strong CW in band signals,  though, are a real
>> pain.
>>>>
>>> <
>>>
>> https://picasaweb.google.com/103357048842463945642/Tronix#607927018804883377
>>>   8
>>> I think that top left board would not be far  away:
>>>
>>> in :  10 MHz LVDS or CMOS
>>> in:   3V3
>>> out: 100 MHz CMOS 3V3
>>>
>>> just a  few hours wall  clock time from layout to working as a
>>> ham radio weekender,  so  please excuse my diy home board
>>> production process.
>>>
>>>   Ok, the use  of a 4046 descendant may not be the last word
>>> from a  timenut perspective,  but I'll redo it with an osc of
>>> my own  anyway. Divider 100/10 is a LVC163  (161?) +  lvc04.
>>>
>>>
>>> <   http://www.crystek.com/crystal/spec-sheets/vcxo/CVHD-950.pdf   >
>>>
>>> Digi-Key has 153 of them on a tape and  441 of a  similar one  , even
>>> cheaper that seems to point to the same data  sheet.
>>>
>>> <
>>>
>> http://www.digikey.de/product-detail/de/CVHD-950-100.000/744-1213-ND/1644128
>>>   You can get the few dB missing close-in by transfer from your
>> reference.
>>> In the picture:
>>> The bottom row of boards is  a doubler  100->200 MHz using 2*BF862,
>> slight
>>> gain,
>>>   and diode doubler 200 ->  400 MHz, SAW filter to get rid of
>>>   100/200/300/500/600 +/-10  etc,
>>> post amp to get a usable level  again.
>>>
>>> Still missing  400-> 800, 800->1600 to  feed  _my_ ADC clock input..
>>>
>>> regards,   Gerhard
>>>
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