[time-nuts] GPS message jitter (was GPS for Nixie Clock)

David davidwhess at gmail.com
Mon Jul 18 15:35:39 EDT 2016

On Mon, 18 Jul 2016 11:43:32 -0700, you wrote:

>except that virtually every UART in use today has some sort of buffering 
>(whether a FIFO or double buffering) between the CPU interface and the 
>bits on the wire, which completely desynchronizes the bits on the wire 
>from the CPU interface.
>Determinism in UART timing between the CPU bus interface and the "bits 
>on the wire" has never been something that is specified.  You can go 
>back to venerable parts like the 8251, and there's no spec in the data 
>( there's a tCR specified as 16 tCY for the read setup time from CTS*, 
>DSR* to READ* assert.  And tSRX (2 usec min) and tHRX (2 usec min) for 
>the setup and hold of the internal sampling pulse relative to RxD. And 
>20 tCY as a max from center of stop bit to RxRDY, and then whatever the 
>delay is from the internal RxRDY to the bus read)

Long ago I remember seeing a circuit design or application note using
an 8250 or similar where the UART start bit was gated so that the
leading edge could be used for precision synchronization.

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