[time-nuts] GPS message jitter (was GPS for Nixie Clock)
scott.j.stobbe at gmail.com
Mon Jul 18 23:42:34 EDT 2016
I can't speak for linux, but I have been bitten by FIFO watermark
interrupts on micros before. If you set an interrupt for a 3/4 full FIFO,
the last one or two characters will sit in the receive buffer and never
trigger the RX interrupt. For a command -> response device which doesn't
have a constant data-stream, It isn't until a PC application resends the
command sequence that enough characters are in the FIFO to trigger the
watermark interrupt. The easy fix was to interrupt on any single character
being available, but would have been nice to have a timeout interrupt on a
partially full FIFO.
On Mon, Jul 18, 2016 at 9:59 PM, Hal Murray <hmurray at megapathdsl.net> wrote:
> jimlux at earthlink.net said:
> > except that virtually every UART in use today has some sort of buffering
> > (whether a FIFO or double buffering) between the CPU interface and the
> > on the wire, which completely desynchronizes the bits on the wire from
> > CPU interface.
> The idea was to reduce the CPU load processing interrupts by batching
> Some of those chips generate an interrupt when the see a return or
> Most of them have an option to disable that batching. On Linux the
> command has a low_latency option. I haven't measured the difference. It
> would be a fun experiment.
> These are my opinions. I hate spam.
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