[time-nuts] Syncing Tom's PICDivs to 1PPS
Tom Van Baak
tvb at LeapSecond.com
Thu Jul 21 11:42:53 EDT 2016
Many of the PIC divider programs that I wrote include an arm-sync feature, which is useful to capture a 1PPS and align the divider to UTC. The source code to most of them are at http://leapsecond.com/pic/src/ and you can use it as a model.
These make use of the fact that PIC 12F-series chips have constant ISR latency so the alignment is perfect to within one PIC instruction, which is four 10 MHz clock cycles. So that's nice, but "perfect" does not mean zero. This is true for all dividers I've seen. The hp 5071A cesium clock does not (can not) sync to nanosecond perfect alignment either. Even if you used an FPGA, a 10 MHz clock still leaves up to 100 ns error in the sync. You get the idea.
If you were doing it all in h/w you could arrange to reset the entire 10^7 synchronous divider chain to under 1 cycle, and then either re-clock the Nth cycle as the 1PPS, or add delays so that N-1th pulse to becomes the 1PPS. It all depends on how picky you want to be about gate delays.
In practice what GPSDO often do is artificially steer the OCXO at some frequency offset for some duration in order to move the phase of the 1PPS. For example, if you run the OCXO fast by 1e-9 for a minute, you have now moved the 1PPS phase ahead by 60 ns.
That means syncing a GPSDO is a two step process. 1) get it to with one or a couple of cycles by zeroing the divider chain, and then 2) get it to within one or a couple of ns by steering the OCXO for a calculated duration. This also implies that the internal TIC has ns resolution and many hundreds of ns range.
----- Original Message -----
From: "Bob Stewart" <bob at evoria.net>
To: "Discussion of Precise Time and Frequency Measurement" <time-nuts at febo.com>
Sent: Wednesday, July 20, 2016 9:11 PM
Subject: [time-nuts] Syncing Tom's PICDivs to 1PPS
For my next GPSDO board revision, I would like to include one of Tom's PICDiv devices to give a much better 1PPS out than the Ublox receivers are capable of. This means that it has to be started (or slewed to be) exactly on time. So I was wondering if anyone had experimented in controlling the startup of one of these PICDivs to make them in sync, and if you'd be willing to share your solution before I start digging into it. I haven't yet looked at the source code for any of these devices, but it's my understanding that this feature isn't provided, and is deemed to be difficult due to the input divider making for a large steering step. Even a suggestion as to which of the chips would be the best candidate would be much appreciated. I'm looking for a method that's deterministic, rather than starving the PICDiv of clock cycles and waiting for the 1PPS to match a conveniently correct 1PPS from the Ublox.
Bob - AE6RV
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