[time-nuts] u-blox "naked" chips - anyone brave enough to try them?
kb8tq at n1k.org
Wed Jun 15 18:43:38 EDT 2016
> On Jun 15, 2016, at 9:22 AM, Attila Kinali <attila at kinali.ch> wrote:
> On Wed, 15 Jun 2016 07:03:28 -0400
> Bob Camp <kb8tq at n1k.org> wrote:
>> If you feed the chip with your local reference:
>> 1) You need to synthesize a signal at the expected frequency (26 MHz, 48 MHz … whatever)
> 26MHz is rather benign to generate. Either use TCXO that has already
> 26MHz (e.g. ASVTX-09 from Abracon are readily available) or lock some VCXO
> to an OCXO of your choise using a simple divider+XOR based PLL.
> If you feel like it you could even use a tiny FPGA (ICE40 come to mind)
> to implement the PLL and get more flexibility.
>> 2) The signal needs to be low phase noise (per the chip set specs)
> The specs of the oscillator used in the LEA modules is pretty much standard.
> Not a great oscillator, but not a bad one either. The above mentioned
> ASVTX-09 is in the same ballpark.
>> 3) The signal needs to be constrained for ADEV (per the chip set specs)
> Same as above.
> If you lock the VCXO to an OCXO, this will be much better.
Each time you steer the OCXO to lock things up, you will degrade both it’s ADEV and it’s
phase noise. If the GPS drops out when you do this …. the GPSDO never locks up.
> Attila Kinali
> It is upon moral qualities that a society is ultimately founded. All
> the prosperity and technological sophistication in the world is of no
> use without that foundation.
> -- Miss Matheson, The Diamond Age, Neil Stephenson
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