[time-nuts] DIY TimePod

Bob Camp kb8tq at n1k.org
Mon Jun 13 15:51:49 EDT 2016


Hi

The ECL inputs will be about 20 db more noisy than the CMOS inputs.

Some phase noise math:

The reference for phase noise is one radian. Yes, that seems a bit odd, but it’s phase modulation so that is the way it works. 

If you are looking at a waveform with a period of 100 ns, your “one radian” will be about 15.9 ns. The “signal” you are after is (say) 
100  db down from 15.9 ns. 

Bob

> On Jun 13, 2016, at 12:54 PM, John Swenson <johnswenson1 at comcast.net> wrote:
> 
> The sampling will be done by a set of ECL flops. The FPGA is reading the already sampled ECL outputs. (with ECL to CMOS converters) I'm using a hex ECL register with one clock input for all six flops,
> 
> The ECL input circuit is a differential amplifier, I will be feeding the CMOS level input to one side and the other side will be a very low noise reference voltage set to half the CMOS voltage (1.65V for 3.3V square wave).
> 
> I really don't know the input noise of that differential amp, but it is probably much better than a normal CMOS input. I guess I will find out!
> 
> The particular chip says it has a max of 100fs additive jitter on the output from the input clock. But that is output jitter, I don't really care about output jitter, it is sampling jitter that is important here, I'm not sure how those two correlate.
> 
> John S.
> 
> On 6/13/2016 6:28 AM, Chris Caudle wrote:
>> On Sun, June 12, 2016 10:50 pm, John Swenson wrote:
>>> I'm just doing phase noise measurements of digital clocks (square waves)
>>> so it seems to me I don't need some of the circuitry in the TimePod, in
>>> particular the digitally controlled RF attenuators and the ADCs
>>> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
>>> reference clocks, convert the differential outputs to CMOS and feed the
>>> FPGA inputs from that. Yes you loose AM noise riding on top of the
>>> square wave, but is that really necessary for just square wave phase
>>> noise measurements?
>> 
>> Are the FPGA inputs low enough noise for that?  With an ADC the time
>> resolution is a combination of clock noise and input noise, for most high
>> quality ADC the effective time resolution you can achieve by analyzing the
>> output data stream is much higher than the resolution of the clock period.
>> Can you achieve similar with just a single bit quantizer based on the FPGA
>> CMOS inputs?
>> 
>> 
> 
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