[time-nuts] DIY TimePod

John Swenson johnswenson1 at comcast.net
Mon Jun 13 21:35:56 EDT 2016


But it is a separate ECL hex flip-flop chip fed by its own ultra low 
noise regulator, not going directly into the FPGA.

John S.



On 6/13/2016 4:51 PM, Bob Camp wrote:
> Hi
>
> ….. but …. The ECL inputs to an FPGA rarely do have lower noise.
>
> Bob
>
>> On Jun 13, 2016, at 6:59 PM, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
>>
>> In order to extract useful information with a 1 bit ADC, the signal transition region needs to be adequately sampled. Issues such as metastability need to be addressed to ensure that useful phase noise noise data can be extracted.
>> There is some evidence (from NIST and elsewhere) that ECL can have lower phase noise than CMOS at low offset frequencies.
>> Bruce
>>
>>
>>     On Monday, 13 June 2016 8:12 PM, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
>>
>>
>> Adjusting the sampling clock frequency so that is neither a harmonic nor a harmonic of a subharmonic of either of the clock frequencies being compared ensures that each clock waveform isnt repeatedly sampled at a small set of  points.i.e.
>> fsample != (m/n)*ftest
>> andfsample != (p/q)*freference
>> where m,n,p,q are integers.
>> When using a dual reference the difference between the frequencies of the pair of reference sources should be significantly less than the lowest offset frequency of interest.
>> Bruce
>>
>>
>>      On Monday, 13 June 2016 6:00 PM, John Swenson <johnswenson1 at comcast.net> wrote:
>>
>>
>> Hi TimeNuts, this is my first post to this list, I've been reading it
>> for years but haven't needed to post, now I'm starting a project and
>> need some advice.
>>
>> I need to do a bunch of phase noise measurements but can't afford the
>> "big guys", the TimePod seems perfect and since the schematic has been
>> published I decided I would try my hand at making my own version.
>>
>> I'm just doing phase noise measurements of digital clocks (square waves)
>> so it seems to me I don't need some of the circuitry in the TimePod, in
>> particular the digitally controlled RF attenuators and the ADCs
>> themselves. My idea is to use LVPECL flip-flops to sample the DUT and
>> reference clocks, convert the differential outputs to CMOS and feed the
>> FPGA inputs from that. Yes you loose AM noise riding on top of the
>> square wave, but is that really necessary for just square wave phase
>> noise measurements?
>>
>> For a first pass cheap and dirty version of this I was planning on using
>> the LVPECL version of the Crystek 575 for the sample clock, will this
>> work? The TimePod schematic shows a VTUNE signal fed to the OCXO, if I
>> don't use that is something going to break? In other words will timelab
>> try and tweak the sample freaquency and get confused when nothing happens?
>>
>> I plan on using the 2 reference clock measurement technique, but have a
>> couple questions about this. In the TimePod ch 0 and 2 are the input,
>> with separate jacks available. The "ref" input goes to ch 1 and 3. So it
>> looks like the two references have to go to 0 and 2 and the DUT to 1 and
>> 3, even though that puts the references on the "input" and the DUT on
>> the "reference". Do you need to do anything special in TimeLab to
>> support this or does it automatically support it? Since I am doing my
>> own hardware and have four independent inputs do I do the same thing
>> (ref clocks on 0 and 2 and DUT on 1 and 3) or put the refs on 1 and 3
>> and the DUT on 0 and 2?
>>
>> Any thoughts?
>>
>> Thanks,
>>
>> John S.
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