[time-nuts] DIY TimePod
bruce.griffiths at xtra.co.nz
Mon Jun 13 22:11:41 EDT 2016
The subsequent all digital mixdown and low pass filtering, if done correctly, will increase the resolution provided that the signal and reference periods are uniformly sampled at a sufficient equivalent number of points. But with a starting point some 70dB or more behind an ADC, the system noise floor wont be particularly low.
On Tuesday, 14 June 2016 1:28 PM, Chris Caudle <chris at chriscaudle.org> wrote:
On Mon, June 13, 2016 6:51 pm, Bob Camp wrote:
> ... The ECL inputs to an FPGA rarely do have lower noise.
I was confused about that at first, the original poster was using external
ECL receivers for sampling, but had CMOS outputs to transmit the data to
That sounds to me like a one bit quantizer, which has approximately 6dB
dynamic range (neglecting for the moment things such as non-linearity and
aliasing). I don't see how you get any decent resolution of where the
edge transition actually occurs.
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