[time-nuts] Commercial software defined radio for clock metrology

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sat May 28 00:52:44 EDT 2016


The first version of the Red Pitaya apparently used an  LTC2145 dual input 14 bit ADC with an SNR of around 72dB (11.6 bits) or so. Various claims of 10 bits effective implies that poor layout, and/or a noisy sampling clock, and/or the analog front end degrade the performance somewhat. For this particular application a noisy sampling clock may  be less of an issue as it is common to both ADC channels.
The Red Pitaya FPGA has about 1/2 the number of logic cells of the FPGA used in the Ettus 210 used in the paper.
The internal sampling jitter of the Ltc2145 appears to be somewhat lower than that of the TI ADC used in the ETTUS 210 SDR. 

Bruce
 

    On Saturday, 28 May 2016 3:08 PM, Bruce Griffiths <bruce.griffiths at xtra..co.nz> wrote:
 

 The Red Pitaya FPGA may be a little too small.Its not clear if a single chip ADC is used.If not, the performance will suffer.Dc coupled inputs will degrade the performance somewhat compared to transformer coupled inputs.

Input bandwidth would be around 40MHz or so for the Nyquist band of interest.The output bandwidth used was something like 100 kHz.
Bruce
 

    On Saturday, 28 May 2016 2:01 PM, Hal Murray <hmurray at megapathdsl.net> wrote:
 

 
bruce.griffiths at xtra.co.nz said:
> All the filtering and down mixing is done in the digital domain.
> Anitialiasing filters in front of the ADCs are also be required. 

What sort of bandwidth is expected?

The usual trick with audio ADCs is to have a low cost analog filter that 
does't have a sharp corner but lets everything you want through, sample at a 
high rate - say 16x, run that through a digital filter with a sharp cutoff, 
then decimate down to the desired sample rate.

-- 
These are my opinions.  I hate spam.



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