[time-nuts] precision timing pulse

Gerhard Hoffmann dk4xp at arcor.de
Thu Nov 17 22:35:55 EST 2016

Am 18.11.2016 um 02:18 schrieb Bob Camp:

> If you head of into ARM land (or even FPGA’s) there is a bit of a gotcha. If you
> want to run a 10 MHz input and a PPS output, you need a counter with at least
> 24 bits. The peripherals on ARM chips are all over the place. Some have very
> fancy timers, but only go to 16 bits. Some have 32 bit timers that aren’t very fancy.
> Some timers will clock at the input clock frequency. Others have weird pre-scale
> rules on them. Since the pre-scaler is a “can’t get at it” device in terms of restarting,
> it puts some limits on what you can do.  With FPGA’s it’s rare to get a 1 pps divider
> and all of the other stuff you want to do in less than about 64 flip flops. That’s not
> a crazy thing on modern parts. It can be an issue on older parts.

The Xilinx XC2064 with 64 FlipFlops is 30 years old or so, RIP!
I don't think that you get FPGAs with less than 10000 flip flops nowadays.


  Design Name         ocxo_carrier
  Fitting Status          Successful
  Software Version   P.20131013
  Device Used          XC2C64A-5-VQ44
  Date                      10-30-2016, 12:51PM

Macrocells         Used Pterms        Used Registers       Used 
Pins        Used Function Block Inputs
50/64  (79%)     157/224  (71%)     50/64  (79%)          7/33 (22%)     
87/160  (55%)

That is about the smallest thing made by Xilinx that you can buy.
It's a CPLD, not even a FPGA.  It runs at 100 MHz, with some care at 200 
and provides the 1pps on my crystal oven carrier board. It also has the
phase detector to lock the oscillator to an incoming 1pps when locking to
a 5/10 MHz reference frequency   or running free   is not wanted.

Source code is about one page all in all.

and the picture to the right.

In the top left corner of the board is some space for an alternate PICDIV.

(For 200 MHz the CPLD needs a beautiful clock signal.)

I have made a design with 2 of these (or one 2C128) that produces one 
fixed 1pps
from a 200 MHz clock and another 1pps that can be shifted over > 1 
second in 5 ns steps,
with an interface to a BeagleBoneBlack to receive control  and enough 
outputs to
steer some switchable ECL delay lines for 5 ps fine steps.

A 2C64 is $1.50 or so.

regards, Gerhard

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